Hi, This series enables the 1-bit inline DDR ECC support in the TI DDRSS bridge for AM62x. The base DDRSS ECC support was merged for k3-ddrss in a previous series for AM64x [1].
The ECC data is stored together with the data, which will reduce the total available memory with 1/9th. The k3-ddrss driver enables the ECC support and primes the full memory from the R5 SPL, so the the memory size changes must propagate from the R5 SPL to A53 SPL and then to A53 u-boot. The patches are similar to those we have for AM64x, with one exception: "arm: mach-k3: common: Use ddr_init in spl_enable_dcache". Since we've switched the boards to DT to fetch the memory configuration, dram_init_banksize() will no longer set the total memory size in the global data. And spl_enable_dcache() uses dram_init_banksize() instead of dram_init(), which actually sets the memory base/size. Note this doesn't enable the 1-bit ECC on any platform by default. This can be done by adding the "ti,ecc-enable" property to the memorycontroller node in k3-am6*-ddr.dtsi. [1] https://lore.kernel.org/u-boot/20220317170346.31162-1-d-gerl...@ti.com/ The patches depend on the base AM62 support, which was recently merged in u-boot/next. Georgi Vlaev (5): arm: mach-k3: common: Use ddr_init in spl_enable_dcache arm: dts: k3-am625-*: Mark memory with u-boot,dm-spl board: ti: am62x: Use fdt functions for ram and bank init board: ti: am62x: Account for DDR size fixups if ECC is enabled configs: am62x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-u-boot.dtsi | 4 ++ arch/arm/mach-k3/common.c | 2 +- board/ti/am62x/evm.c | 62 ++++++++++++++++++++++++---- configs/am62x_evm_r5_defconfig | 1 + 5 files changed, 61 insertions(+), 9 deletions(-) base-commit: a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74 -- 2.30.2
