[PATCH 04/13] watchdog: designware: Make this depend on WDT

[Tom Rini]

As this driver can dynamically determine the values set in
CONFIG_DW_WDT_BASE when using WDT, so make this depend on WDT rather
than migrate CONFIG_DW_WDT_BASE to Kconfig.

Cc: Chee Tien Fong <tien.fong.c...@intel.com>
Cc: Chin-Liang See <chin.liang....@intel.com>
Cc: Dinh Nguyen <dinh.ngu...@intel.com>
Cc: Holger Brunck <holger.bru...@hitachienergy.com>
Cc: Ley Foon Tan <ley.foon....@intel.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Siew Chin Lim <elly.siew.chin....@intel.com>
Cc: Stefan Roese <s...@denx.de>
Cc: hee Hong Ang <chee.hong....@intel.com>
Signed-off-by: Tom Rini <tr...@konsulko.com>
---
 drivers/watchdog/Kconfig               |  4 ++--
 drivers/watchdog/designware_wdt.c      | 21 ---------------------
 include/configs/socfpga_common.h       |  1 -
 include/configs/socfpga_soc64_common.h |  1 -
 4 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c3eb8a8aec1b..532ada89c1b2 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -64,8 +64,8 @@ config ULP_WATCHDOG
 
 config DESIGNWARE_WATCHDOG
        bool "Designware watchdog timer support"
-       select HW_WATCHDOG if !WDT
-       default y if WDT && ROCKCHIP_RK3399
+       depends on WDT
+       default y if ROCKCHIP_RK3399
        help
          Enable this to support Designware Watchdog Timer IP, present e.g.
          on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/designware_wdt.c 
b/drivers/watchdog/designware_wdt.c
index cfec29bd158c..cad756aeaf20 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -60,26 +60,6 @@ static void designware_wdt_reset_common(void __iomem *base)
                writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
 }
 
-#if !CONFIG_IS_ENABLED(WDT)
-void hw_watchdog_reset(void)
-{
-       designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
-}
-
-void hw_watchdog_init(void)
-{
-       /* reset to disable the watchdog */
-       hw_watchdog_reset();
-       /* set timer in miliseconds */
-       designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
-                                 CONFIG_DW_WDT_CLOCK_KHZ,
-                                 CONFIG_WATCHDOG_TIMEOUT_MSECS);
-       /* enable the watchdog */
-       designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
-       /* reset the watchdog */
-       hw_watchdog_reset();
-}
-#else
 static int designware_wdt_reset(struct udevice *dev)
 {
        struct designware_wdt_priv *priv = dev_get_priv(dev);
@@ -195,4 +175,3 @@ U_BOOT_DRIVER(designware_wdt) = {
        .ops = &designware_wdt_ops,
        .flags = DM_FLAG_PRE_RELOC,
 };
-#endif
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d1efba29fc40..4a7da76e51e6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -66,7 +66,6 @@
 /*
  * L4 Watchdog
  */
-#define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ                25000
 
 /*
diff --git a/include/configs/socfpga_soc64_common.h 
b/include/configs/socfpga_soc64_common.h
index c1037ab595fa..a3e8d5492919 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -92,7 +92,6 @@
 /*
  * L4 Watchdog
  */
-#define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 #ifndef __ASSEMBLY__
 unsigned int cm_get_l4_sys_free_clk_hz(void);
-- 
2.25.1