On Sun, Jun 26, 2022 at 6:42 PM Patrick Wildt <patr...@blueri.se> wrote:
> +static iomux_v3_cfg_t const uart_pads[] = { > + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; As you use DM_SERIAL, this is no longer necessary. > +int board_phy_config(struct phy_device *phydev) > +{ > + int val; > + > + /* > + * Ar803x phy SmartEEE feature cause link status generates glitch, > + * which cause ethernet link down/up issue, so disable SmartEEE > + */ > + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); > + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); > + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); > + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); > + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val & ~(1 << 8)); > + > + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); > + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); > + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); > + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); > + val &= ~0x11c; > + val |= 0x80; /* 1/2 drive strength */ > + val |= 0x18; /* 125 MHz */ > + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); > + > + /* rgmii tx clock delay enable */ > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); > + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val | 0x0100); It seems the PHY code could be removed in favor of DM. > +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) With DM, this is not needed.