Add a "secure" version of STM32 boards based on SCMI when RCC_TZCR.TZEN=1.
Only boards provided by STMicroelectronics are concerned:
-STM32MP157A-DK1
-STM32MP157C-DK2
-STM32MP157C-ED1
-STM32MP157C-EV1
The resources secured by RCC_TZCR.TZEN=1 are managed by OP-TEE
and the associated SCMI services, reset and clock.
These device trees are only supported with stm32mp15_defconfig,
with OP-TEE, SCMI and without SPL support.
Signed-off-by: Patrick Delaunay <patrick.delau...@foss.st.com>
---
arch/arm/dts/Makefile | 4 +
arch/arm/dts/stm32mp15-scmi-u-boot.dtsi | 167 ++++++++++++++++++
arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 57 ++++++
arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 47 +++++
arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi | 17 ++
doc/board/st/stm32mp1.rst | 19 ++
7 files changed, 317 insertions(+)
create mode 100644 arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 87b210dbb01..a6b5295afc3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1171,13 +1171,17 @@ dtb-$(CONFIG_STM32MP13x) += \
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
+ stm32mp157a-dk1-scmi.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157c-dk2.dtb \
+ stm32mp157c-dk2-scmi.dtb \
stm32mp157c-ed1.dtb \
+ stm32mp157c-ed1-scmi.dtb \
stm32mp157c-ev1.dtb \
+ stm32mp157c-ev1-scmi.dtb \
stm32mp157c-odyssey.dtb \
stm32mp15xx-dhcom-drc02.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
diff --git a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
new file mode 100644
index 00000000000..314fc39a054
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ gpio25 = &gpioz;
+ pinctrl0 = &pinctrl;
+ pinctrl1 = &pinctrl_z;
+ };
+
+ binman: binman {
+ multiple-images;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ddr: ddr@5a003000 {
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp1-ddr";
+
+ reg = <0x5a003000 0x550
+ 0x5a004000 0x234>;
+
+ status = "okay";
+ };
+ };
+
+ /* need PSCI for sysreset during board_f */
+ psci {
+ u-boot,dm-pre-proper;
+ };
+};
+
+&bsec {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioz {
+ u-boot,dm-pre-reloc;
+};
+
+&optee {
+ u-boot,dm-pre-proper;
+};
+
+&iwdg2 {
+ u-boot,dm-pre-reloc;
+};
+
+/* pre-reloc probe = reserve video frame buffer in video_reserve() */
+<dc {
+ u-boot,dm-pre-proper;
+};
+
+/* temp = waiting kernel update */
+&m4_rproc {
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&scmi {
+ u-boot,dm-pre-proper;
+};
+
+&usart1 {
+ resets = <&rcc USART1_R>;
+};
+
+&usart2 {
+ resets = <&rcc USART2_R>;
+};
+
+&usart3 {
+ resets = <&rcc USART3_R>;
+};
+
+&uart4 {
+ resets = <&rcc UART4_R>;
+};
+
+&uart5 {
+ resets = <&rcc UART5_R>;
+};
+
+&usart6 {
+ resets = <&rcc USART6_R>;
+};
+
+&uart7 {
+ resets = <&rcc UART7_R>;
+};
+
+&uart8{
+ resets = <&rcc UART8_R>;
+};
diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
new file mode 100644
index 00000000000..2db045e7cec
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2022
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-scmi-u-boot.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+
+/ {
+ aliases {
+ i2c3 = &i2c4;
+ usb0 = &usbotg_hs;
+ };
+
+ config {
+ u-boot,boot-led = "heartbeat";
+ u-boot,error-led = "error";
+ u-boot,mmc-env-partition = "u-boot-env";
+ st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
+ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
+ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
+ };
+
+ led {
+ red {
+ label = "error";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ status = "okay";
+ };
+ };
+};
+
+&adc {
+ status = "okay";
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
+ };
+};
+
+&usbotg_hs {
+ u-boot,force-b-session-valid;
+};
diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
new file mode 100644
index 00000000000..5a8fc15ab2b
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2022
+ */
+
+#include "stm32mp157a-dk1-scmi-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
new file mode 100644
index 00000000000..54662f7e290
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2022
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-scmi-u-boot.dtsi"
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+
+/ {
+ aliases {
+ i2c3 = &i2c4;
+ };
+
+ config {
+ u-boot,boot-led = "heartbeat";
+ u-boot,error-led = "error";
+ u-boot,mmc-env-partition = "u-boot-env";
+ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
+ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
+ };
+
+ led {
+ red {
+ label = "error";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ status = "okay";
+ };
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
new file mode 100644
index 00000000000..71a94f9130a
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2022
+ */
+
+#include "stm32mp157c-ed1-scmi-u-boot.dtsi"
+
+/ {
+ aliases {
+ gpio26 = &stmfx_pinctrl;
+ i2c1 = &i2c2;
+ i2c4 = &i2c5;
+ pinctrl2 = &stmfx_pinctrl;
+ spi0 = &qspi;
+ usb0 = &usbotg_hs;
+ };
+};
diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
index 00f9b454421..3759df353ee 100644
--- a/doc/board/st/stm32mp1.rst
+++ b/doc/board/st/stm32mp1.rst
@@ -77,6 +77,16 @@ Currently the following boards are supported:
+ stm32mp157c-ev1.dts
+ stm32mp15xx-dhcor-avenger96.dts
+The SCMI variant of each board is supported by a specific "scmi" device tree:
+ + stm32mp157a-dk1-scmi.dts
+ + stm32mp157c-dk2-scmi.dts
+ + stm32mp157c-ed1-scmi.dts
+ + stm32mp157c-ev1-scmi.dts
+
+SCMI variant is used only with stm32mp15_defconfig, when the resources are
+secured with RCC_TZCR.TZEN=1 in OP-TEE. The access to these reset and clock
+resources are provided by OP-TEE and the associated SCMI services.
+
STM32MP13x
``````````
@@ -136,6 +146,9 @@ TF-A_ (BL2) initialize the DDR and loads the next stage
binaries from a FIP file
the secure monitor to access to secure resources.
+ HW_CONFIG: The hardware configuration file = the U-Boot device tree
+The scmi variant of each device tree is only support with OP-TEE as secure
+monitor, with stm32mp15_defconfig.
+
The **Basic** boot chain with SPL (for STM32MP15x)
``````````````````````````````````````````````````
@@ -248,6 +261,12 @@ Build Procedure
a) trusted boot with FIP on STM32MP15x ev1::
+ # export KBUILD_OUTPUT=stm32mp15
+ # make stm32mp15_defconfig
+ # make DEVICE_TREE=stm32mp157c-ev1-scmi all
+
+ or without SCMI support
+
# export KBUILD_OUTPUT=stm32mp15
# make stm32mp15_defconfig
# make DEVICE_TREE=stm32mp157c-ev1 all
--
2.25.1
