From: Christian Kohn <christian.k...@xilinx.com>
The fclk-enable property is set to 0 which disables all FCLKs.
Enable all FCLKs so they can be used as clock sources in the
programmable logic.
Signed-off-by: Christian Kohn <christian.k...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@amd.com>
---
arch/arm/dts/zynq-7000.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 37155df0fd42..9626a0714625 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -329,7 +329,7 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- fclk-enable = <0>;
+ fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x",
"cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap",
"gem0", "gem1",
--
2.36.1
