On Thursday 14 July 2022 01:50:44 Pali Rohár wrote:
> On Tuesday 28 June 2022 20:14:36 Pali Rohár wrote:
> > On Thursday 23 June 2022 15:31:14 Pali Rohár wrote:
> > > On Monday 20 June 2022 12:54:26 Pali Rohár wrote:
> > > > This allows to concatenate SPL and proper U-Boot without extra
> > > > alignment.
> > > >
> > > > Signed-off-by: Pali Rohár <p...@kernel.org>
> > > > ---
> > > > Changes in v2:
> > > > * Rebased on top of the U-Boot next branch, commit
> > > > 98c4828740f4944462b7d9608b95d5b73850c7b0
> > >
> > > PING?
> >
> > PING?
>
> PING?
PING? What is happening here? I have not received any reply for this
patch for more than month. You asked me for rebasing more patches, I did
it in one day since request and get no reply.
> > > > ---
> > > > drivers/mmc/fsl_esdhc_spl.c | 27 +++++++++++++++++++++++----
> > > > 1 file changed, 23 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
> > > > index 760f13d24018..54bf8152ca7a 100644
> > > > --- a/drivers/mmc/fsl_esdhc_spl.c
> > > > +++ b/drivers/mmc/fsl_esdhc_spl.c
> > > > @@ -58,10 +58,10 @@ void __noreturn mmc_boot(void)
> > > > {
> > > > __attribute__((noreturn)) void (*uboot)(void);
> > > > uint blk_start, blk_cnt, err;
> > > > + u32 blk_off;
> > > > #ifndef CONFIG_FSL_CORENET
> > > > uchar *tmp_buf;
> > > > u32 blklen;
> > > > - u32 blk_off;
> > > > uchar val;
> > > > #ifndef CONFIG_SPL_FSL_PBL
> > > > u32 val32;
> > > > @@ -155,10 +155,21 @@ again:
> > > > * Load U-Boot image from mmc into RAM
> > > > */
> > > > code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
> > > > - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
> > > > - blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
> > > > + blk_start = offset / mmc->read_bl_len;
> > > > + blk_off = offset % mmc->read_bl_len;
> > > > + blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len
> > > > + 1;
> > > > + if (blk_off) {
> > > > + err = mmc->block_dev.block_read(&mmc->block_dev,
> > > > + blk_start, 1, tmp_buf);
> > > > + if (err != 1) {
> > > > + puts("spl: mmc read failed!!\n");
> > > > + hang();
> > > > + }
> > > > + blk_start++;
> > > > + }
> > > > err = mmc->block_dev.block_read(&mmc->block_dev, blk_start,
> > > > blk_cnt,
> > > > - (uchar
> > > > *)CONFIG_SYS_MMC_U_BOOT_DST);
> > > > + (uchar
> > > > *)CONFIG_SYS_MMC_U_BOOT_DST +
> > > > + (blk_off ? (mmc->read_bl_len -
> > > > blk_off) : 0));
> > > > if (err != blk_cnt) {
> > > > puts("spl: mmc read failed!!\n");
> > > > #ifndef CONFIG_FSL_CORENET
> > > > @@ -166,6 +177,14 @@ again:
> > > > #endif
> > > > hang();
> > > > }
> > > > + /*
> > > > + * SDHC DMA may erase bytes at dst + bl_len - blk_off - 8
> > > > + * due to unaligned access. So copy leading bytes from tmp_buf
> > > > + * after SDHC DMA transfer.
> > > > + */
> > > > + if (blk_off)
> > > > + memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST,
> > > > + tmp_buf + blk_off, mmc->read_bl_len - blk_off);
> > > >
> > > > /*
> > > > * Clean d-cache and invalidate i-cache, to
> > > > --
> > > > 2.20.1
> > > >
