High row detection for non-8bit bw requires axi split.
So, update the existing high row detection code in order
to support full bw chips.
Signed-off-by: YouMin Chen <c...@rock-chips.com>
Signed-off-by: Jagan Teki <ja...@edgeble.ai>
---
.../include/asm/arch-rockchip/sdram_common.h | 2 +-
drivers/ram/rockchip/sdram_common.c | 56 ++++++++++++++++++-
drivers/ram/rockchip/sdram_px30.c | 2 +-
3 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index a14b37cbc5..dd316f771a 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -136,7 +136,7 @@ int sdram_detect_row(struct sdram_cap_info *cap_info,
u32 coltmp, u32 bktmp, u32 rowtmp);
int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
u32 coltmp, u32 bktmp);
-int sdram_detect_high_row(struct sdram_cap_info *cap_info);
+int sdram_detect_high_row(struct sdram_cap_info *cap_info, u32 dramtype);
int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type);
u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type);
void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n);
diff --git a/drivers/ram/rockchip/sdram_common.c
b/drivers/ram/rockchip/sdram_common.c
index 1c3236746a..17d0096dfd 100644
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
@@ -381,10 +381,60 @@ int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
return 0;
}
-int sdram_detect_high_row(struct sdram_cap_info *cap_info)
+int sdram_detect_high_row(struct sdram_cap_info *cap_info, u32 dramtype)
{
- cap_info->cs0_high16bit_row = cap_info->cs0_row;
- cap_info->cs1_high16bit_row = cap_info->cs1_row;
+ unsigned long base_addr;
+ u32 cs0_high_row, cs1_high_row, cs;
+ u64 cap = 0, cs0_cap = 0;
+ u32 i;
+ void __iomem *test_addr, *test_addr1;
+
+ cs = cap_info->rank;
+ /* 8bit bandwidth no enable axi split*/
+ if (!cap_info->bw) {
+ cs0_high_row = cap_info->cs0_row;
+ cs1_high_row = cap_info->cs1_row;
+ goto out;
+ }
+
+ cs0_cap = sdram_get_cs_cap(cap_info, 0, dramtype);
+ if (cs == 2) {
+ base_addr = CONFIG_SYS_SDRAM_BASE + cs0_cap;
+ cap = sdram_get_cs_cap(cap_info, 1, dramtype);
+ } else {
+ base_addr = CONFIG_SYS_SDRAM_BASE;
+ cap = cs0_cap;
+ }
+ /* detect full bandwidth size */
+ for (i = 0; i < 4; i++) {
+ test_addr = (void __iomem *)base_addr;
+ test_addr1 = (void __iomem *)(base_addr +
+ (unsigned long)(cap / (1ul << (i + 1))));
+ writel(0x0, test_addr);
+ writel(PATTERN, test_addr1);
+ if ((readl(test_addr) == 0x0) &&
+ (readl(test_addr1) == PATTERN))
+ break;
+ }
+ if (i == 4 && cs == 1) {
+ printascii("can't support this cap\n");
+ return -1;
+ }
+
+ if (cs == 2) {
+ cs0_high_row = cap_info->cs0_row;
+ if (i == 4)
+ cs1_high_row = 0;
+ else
+ cs1_high_row = cap_info->cs1_row - i;
+ } else {
+ cs0_high_row = cap_info->cs0_row - i;
+ cs1_high_row = 0;
+ }
+
+out:
+ cap_info->cs0_high16bit_row = cs0_high_row;
+ cap_info->cs1_high16bit_row = cs1_high_row;
return 0;
}
diff --git a/drivers/ram/rockchip/sdram_px30.c
b/drivers/ram/rockchip/sdram_px30.c
index a003893538..6b700f5ce5 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -677,7 +677,7 @@ static int sdram_init_detect(struct dram_info *dram,
writel(sys_reg3, &dram->pmugrf->os_reg[3]);
}
- ret = sdram_detect_high_row(cap_info);
+ ret = sdram_detect_high_row(cap_info, sdram_params->base.dramtype);
out:
return ret;
--
2.25.1
