Hi Weijie, On Wed, 3 Aug 2022 at 21:41, Weijie Gao <weijie....@mediatek.com> wrote: > > This patch adds more nand headers in two new types: > 1. HSM header, used for spi-nand thru SNFI interface > 2. SPIM header, used for spi-nand thru spi-mem interface > > The original nand header is renamed to AP header. > > Signed-off-by: Weijie Gao <weijie....@mediatek.com> > --- > tools/mtk_image.c | 23 ++- > tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++-- > tools/mtk_nand_headers.h | 110 +++++++++- > 3 files changed, 525 insertions(+), 30 deletions(-)
Reviewed-by: Simon Glass <s...@chromium.org> [..] > diff --git a/tools/mtk_nand_headers.h b/tools/mtk_nand_headers.h > index 691db85005..ce4a824e29 100644 > --- a/tools/mtk_nand_headers.h > +++ b/tools/mtk_nand_headers.h > @@ -16,6 +16,7 @@ struct nand_header_info { > uint32_t page_size; > uint32_t spare_size; > uint32_t gfh_offset; > + bool snfi; > }; > > /* AP BROM Header for NAND */ > @@ -39,14 +40,117 @@ union nand_boot_header { > uint8_t data[0x80]; > }; > > +/* HSM BROM Header for NAND */ > +union hsm_nand_boot_header { > + struct { > + char id[8]; > + uint32_t version; > + uint32_t config; > + uint32_t sector_size; > + uint32_t fdm_size; > + uint32_t fdm_ecc_size; > + uint32_t lbs; > + uint32_t page_size; > + uint32_t spare_size; > + uint32_t page_per_block; > + uint32_t blocks; > + uint32_t plane_sel_position; > + uint32_t pll; > + uint32_t acccon; > + uint32_t strobe_sel; > + uint32_t acccon1; > + uint32_t dqs_mux; > + uint32_t dqs_ctrl; > + uint32_t delay_ctrl; > + uint32_t latch_lat; > + uint32_t sample_delay; > + uint32_t driving; > + uint32_t bl_start; > + uint32_t bl_end; > + uint8_t ecc_parity[42]; > + }; > + > + uint8_t data[0x8E]; > +}; > + > +/* HSM2.0 BROM Header for NAND */ > +union hsm20_nand_boot_header { > + struct { > + char id[8]; > + uint32_t version; > + uint32_t config; > + uint32_t sector_size; > + uint32_t fdm_size; > + uint32_t fdm_ecc_size; > + uint32_t lbs; > + uint32_t page_size; > + uint32_t spare_size; > + uint32_t page_per_block; > + uint32_t blocks; > + uint32_t plane_sel_position; > + uint32_t pll; > + uint32_t acccon; > + uint32_t strobe_sel; > + uint32_t acccon1; > + uint32_t dqs_mux; > + uint32_t dqs_ctrl; > + uint32_t delay_ctrl; > + uint32_t latch_lat; > + uint32_t sample_delay; > + uint32_t driving; > + uint32_t reserved; > + uint32_t bl0_start; > + uint32_t bl0_end; > + uint32_t bl0_type; > + uint8_t bl_reserve[84]; > + uint8_t ecc_parity[42]; > + }; > + > + uint8_t data[0xEA]; > +}; > + > +/* SPIM BROM Header for NAND */ > +union spim_nand_boot_header { > + struct { > + char id[8]; > + uint32_t version; > + uint32_t config; > + uint32_t page_size; > + uint32_t spare_size; > + uint16_t page_per_block; > + uint16_t plane_sel_position; > + uint16_t reserve_reg; > + uint16_t reserve_val; > + uint16_t ecc_error; > + uint16_t ecc_mask; > + uint32_t bl_start; > + uint32_t bl_end; > + uint8_t ecc_parity[32]; > + uint32_t integrity_crc; > + }; > + > + uint8_t data[0x50]; > +}; > + > +enum nand_boot_header_type { > + NAND_BOOT_AP_HEADER, > + NAND_BOOT_HSM_HEADER, > + NAND_BOOT_HSM20_HEADER, > + NAND_BOOT_SPIM_HEADER > +}; > + > #define NAND_BOOT_NAME "BOOTLOADER!" > #define NAND_BOOT_VERSION "V006" > #define NAND_BOOT_ID "NFIINFO" > > -const union nand_boot_header *mtk_nand_header_find(const char *name); > -uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); > +#define HSM_NAND_BOOT_NAME "NANDCFG!" > +#define SPIM_NAND_BOOT_NAME "SPINAND!" > + > +const struct nand_header_type *mtk_nand_header_find(const char *name); > +uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand); > int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); > bool is_mtk_nand_header(const void *ptr); > -uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void > *ptr); > +uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, > + void *ptr); functions and structs need documentation > > #endif /* _MTK_NAND_HEADERS_H */ > -- > 2.17.1 > Regards, Simon