The GW73xx-C revision and onward replaced the 5-port PCIe switch with a
4-port (dropping PCIe to one of the miniPCIe sockets) due to part
availability. This moved the PCI bus of the GbE eth1 device. Use a fixup
to adjust the dt accordingly so that local-mac-address assigned from dt
works on new revision boards.
While we are at it, rename 'blob' to 'fdt' for clarity.
Signed-off-by: Tim Harvey <thar...@gateworks.com>
---
board/gateworks/venice/eeprom.c | 7 ++++++
board/gateworks/venice/eeprom.h | 3 +++
board/gateworks/venice/venice.c | 43 +++++++++++++++++++++++++++------
3 files changed, 46 insertions(+), 7 deletions(-)
diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c
index 7a46f44828ce..ac52cc0a9ec9 100644
--- a/board/gateworks/venice/eeprom.c
+++ b/board/gateworks/venice/eeprom.c
@@ -20,6 +20,7 @@
struct venice_board_info som_info;
struct venice_board_info base_info;
char venice_model[32];
+char venice_baseboard_model[32];
u32 venice_serial;
/* return a mac address from EEPROM info */
@@ -321,6 +322,7 @@ int eeprom_init(int quiet)
base_info.model[3], /* baseboard */
base_info.model[4], base_info.model[5], /* subload of
baseboard */
som_info.model[4], som_info.model[5]); /* last 2digits
of SOM */
+ strlcpy(venice_baseboard_model, base_info.model,
sizeof(venice_baseboard_model));
/* baseboard revision */
rev_pcb = get_pcb_rev(base_info.model);
@@ -357,6 +359,11 @@ const char *eeprom_get_model(void)
return venice_model;
}
+const char *eeprom_get_baseboard_model(void)
+{
+ return venice_baseboard_model;
+}
+
u32 eeprom_get_serial(void)
{
return venice_serial;
diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h
index 37bfe76ad81e..8ea7318d7dfc 100644
--- a/board/gateworks/venice/eeprom.h
+++ b/board/gateworks/venice/eeprom.h
@@ -26,8 +26,11 @@ struct venice_board_info {
int eeprom_init(int quiet);
const char *eeprom_get_model(void);
+const char *eeprom_get_baseboard_model(void);
const char *eeprom_get_dtb_name(int level, char *buf, int len);
int eeprom_getmac(int index, uint8_t *enetaddr);
uint32_t eeprom_get_serial(void);
+int get_bom_rev(const char *str);
+char get_pcb_rev(const char *str);
#endif
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index f1efabb203d7..32b25ffd3edf 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -3,6 +3,7 @@
* Copyright 2021 Gateworks Corporation
*/
+#include <fdt_support.h>
#include <init.h>
#include <led.h>
#include <miiphy.h>
@@ -169,26 +170,54 @@ int board_mmc_get_env_dev(int devno)
return devno;
}
-int ft_board_setup(void *blob, struct bd_info *bd)
+int ft_board_setup(void *fdt, struct bd_info *bd)
{
+ const char *base_model = eeprom_get_baseboard_model();
+ char pcbrev;
int off;
/* set board model dt prop */
- fdt_setprop_string(blob, 0, "board", eeprom_get_model());
+ fdt_setprop_string(fdt, 0, "board", eeprom_get_model());
/* update temp thresholds */
- off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips");
+ off = fdt_path_offset(fdt, "/thermal-zones/cpu-thermal/trips");
if (off >= 0) {
int minc, maxc, prop;
get_cpu_temp_grade(&minc, &maxc);
- fdt_for_each_subnode(prop, blob, off) {
- const char *type = fdt_getprop(blob, prop, "type",
NULL);
+ fdt_for_each_subnode(prop, fdt, off) {
+ const char *type = fdt_getprop(fdt, prop, "type", NULL);
if (type && (!strcmp("critical", type)))
- fdt_setprop_u32(blob, prop, "temperature", maxc
* 1000);
+ fdt_setprop_u32(fdt, prop, "temperature", maxc
* 1000);
else if (type && (!strcmp("passive", type)))
- fdt_setprop_u32(blob, prop, "temperature",
(maxc - 10) * 1000);
+ fdt_setprop_u32(fdt, prop, "temperature", (maxc
- 10) * 1000);
+ }
+ }
+
+ if (!strncmp(base_model, "GW73", 4)) {
+ pcbrev = get_pcb_rev(base_model);
+
+ if (pcbrev > 'B') {
+ printf("adjusting dt for %s\n", base_model);
+
+ /*
+ * revC replaced PCIe 5-port switch with 4-port
+ * which changed ethernet1 PCIe GbE
+ * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
+ * to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
+ */
+ off = fdt_path_offset(fdt, "ethernet1");
+ if (off > 0) {
+ u32 reg[5];
+
+ fdt_set_name(fdt, off, "pcie@5,0");
+ off = fdt_parent_offset(fdt, off);
+ fdt_set_name(fdt, off, "pcie@2,3");
+ memset(reg, 0, sizeof(reg));
+ reg[0] = cpu_to_fdt32(PCI_DEVFN(3, 0));
+ fdt_setprop(fdt, off, "reg", reg, sizeof(reg));
+ }
}
}
--
2.25.1
