From: Chee Hong Ang <chee.hong....@intel.com>
QSPI driver perform chip select on every flash read/write
access. The driver need to disable/enable the QSPI controller
while performing chip select. This may cause some data lost
especially the QSPI controller is configured to run at slower
speed as it may take longer time to access the flash device.
This patch prevent the driver from disable/enable the QSPI
controller too soon and inadvertently halting any ongoing flash
read/write access by ensuring the QSPI controller is always in
idle mode after each read/write access.
Signed-off-by: Chee Hong Ang <chee.hong....@intel.com>
---
drivers/spi/cadence_qspi_apb.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2cdf4c9c9f..5e03495f45 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct
cadence_spi_plat *plat,
writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
- /* Check indirect done status */
- ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
- CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
- if (ret) {
- printf("Indirect read clear completion error (%i)\n", ret);
- goto failrd;
- }
+ /* Wait til QSPI is idle */
+ if (!cadence_qspi_wait_idle(plat->regbase))
+ return -EIO;
return 0;
@@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct
cadence_spi_plat *plat,
if (bounce_buf)
free(bounce_buf);
+
+ /* Wait til QSPI is idle */
+ if (!cadence_qspi_wait_idle(plat->regbase))
+ return -EIO;
+
return 0;
failwr:
--
2.25.1
