on imx8(mm) the RXDMUXSEL needs to be set for data going over the wire
(as observable on a connected 'scope) to actually make it into the
RXFIFO
the reference manual is not overly clear about this, and only
mentiones that "UCR3_RXDMUXSEL should always be set." - and since the
CR3 register reverts to its reset values after setting the baudrate,
setting this bit is done during '_mxc_serial_setbgr'
Signed-off-by: Johannes Schneider <johannes.schnei...@leica-geosystems.com>
Reviewed-by: Peng Fan <peng....@nxp.com>
---
Changes in v4:
- add 'reviewd-by'
Changes in v3:
- more verbose commit messages
Changes in v2:
- manually fix 'to' and 'cc'
- fix comment delimiter
drivers/serial/serial_mxc.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 70a0e5e919..fa344c8b8f 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -61,6 +61,11 @@
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+
+/* imx8 names these bitsfields instead: */
+#define UCR3_DTRDEN BIT(3) /* bit not used in this chip */
+#define UCR3_RXDMUXSEL BIT(2) /* RXD muxed input selected; 'should always be
set' */
+
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
#define UCR3_BPEN (1<<0) /* Preset registers enable */
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
@@ -176,6 +181,13 @@ static void _mxc_serial_setbrg(struct mxc_uart *base,
unsigned long clk,
writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
&base->cr2);
+
+ /* setting the baudrate triggers a reset, returning cr3 to its
+ * reset value but UCR3_RXDMUXSEL "should always be set."
+ * according to the imx8 reference-manual
+ */
+ writel(readl(&base->cr3) | UCR3_RXDMUXSEL, &base->cr3);
+
writel(UCR1_UARTEN, &base->cr1);
}
--
2.25.1
