The GW7902 revision B adds two additional GPIO's to control the
direction of the 2 isolated digital I/O circuits.

Define them as:
 - dig1_ctl
 - dig2_ctl

Signed-off-by: Tim Harvey <thar...@gateworks.com>
---
 arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi | 14 ++++++++++++++
 arch/arm/dts/imx8mm-venice-gw7903.dts         |  4 +++-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi 
b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
index 896e5d4edde3..ff9b12a83408 100644
--- a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
@@ -43,6 +43,20 @@
                line-name = "dig2_out#";
        };
 
+       dig2ctl {
+               gpio-hog;
+               output-low;
+               gpios = <2 GPIO_ACTIVE_HIGH>;
+               line-name = "dig2_ctl";
+       };
+
+       dig1ctl {
+               gpio-hog;
+               output-low;
+               gpios = <6 GPIO_ACTIVE_HIGH>;
+               line-name = "dig1_ctl";
+       };
+
        dig1out {
                gpio-hog;
                output-high;
diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts 
b/arch/arm/dts/imx8mm-venice-gw7903.dts
index a7dae9bd4c11..1b69ac0e12b0 100644
--- a/arch/arm/dts/imx8mm-venice-gw7903.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7903.dts
@@ -250,7 +250,7 @@
 };
 
 &gpio2 {
-       gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
+       gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", 
"dig1_ctl", "",
                "dig1_out#", "dig1_in", "", "", "", "", "", "",
                "", "", "", "", "", "", "", "",
                "", "", "", "", "", "", "", "";
@@ -630,6 +630,8 @@
                        MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x40000041 /* 
RS232# */
                        MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9        0x40000041 /* 
DIG1_IN */
                        MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x40000041 /* 
DIG1_OUT */
+                       MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x40000041 /* 
DIG1_CTL */
+                       MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2        0x40000041 /* 
DIG2_CTL */
                        MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0          0x40000041 /* 
DIG2_IN */
                        MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1          0x40000041 /* 
DIG2_OUT */
                        MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7      0x40000041 /* 
SIM1DET# */
-- 
2.25.1

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