From: Tien Fong Chee <tien.fong.c...@intel.com>
This field allows the FPGA ports to directly access the extra data bits
that are normally used to hold the ECC code, so this field must be clear
when it's used for ECC data.
Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
Signed-off-by: Teik Heng Chong <teik.heng.ch...@intel.com>
---
drivers/ddr/altera/sdram_gen5.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 9d69f009e9..085d146179 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -659,6 +659,9 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
debug("SDRAM: %ld MiB\n", sdram_size >> 20);
if (sdram_is_ecc_enabled(sdr_ctrl)) {
+ /* Must set USEECCASDATA to 0 if ECC is enabled */
+ clrbits_le32(&sdr_ctrl->static_cfg,
+ SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK);
sdram_init_ecc_bits(sdram_size);
}
--
2.26.2
