On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese <s...@denx.de> wrote:
>
> On 21.09.22 06:59, Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
> > has been ported from Marvell's SDK which is based on a much older
> > version of U-Boot.
> >
> > Signed-off-by: Chris Packham <judge.pack...@gmail.com>
> > ---
> >
<snip>
> > diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c
> > b/arch/arm/mach-mvebu/alleycat5/soc.c
> > new file mode 100644
> > index 0000000000..f388d4ee40
> > --- /dev/null
> > +++ b/arch/arm/mach-mvebu/alleycat5/soc.c
<snip>
> > +/* Return NAND clock in Hz */
> > +u32 mvebu_get_nand_clock(void)
> > +{
> > + return 200 * 1000000;
> > +}
>
> Is this still needed?
>
It will be needed eventually. After I get this landed I'll start work
on getting our board upstreamed and that does make use of the NAND
interface. There are some NAND driver changes that go along with this
so I'll move this over into that patch series.
