On Mon, Sep 19, 2022 at 05:19:07PM +0530, Kautuk Consul wrote: > We add RISC-V semihosting based serial console for JTAG based early > debugging. > > The RISC-V semihosting specification is available at: > https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc > > Signed-off-by: Anup Patel <apa...@ventanamicro.com> > Signed-off-by: Kautuk Consul <kcon...@ventanamicro.com> > --- > arch/riscv/include/asm/spl.h | 1 + > arch/riscv/lib/Makefile | 2 ++ > arch/riscv/lib/interrupts.c | 11 +++++++++++ > arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++ > lib/Kconfig | 6 +++--- > 5 files changed, 41 insertions(+), 3 deletions(-) > create mode 100644 arch/riscv/lib/semihosting.c
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>