From: Dave Gerlach <d-gerl...@ti.com>
Move k3-am64-sk to use 1600MT/s LPDDR4 configuration and update to latest EMIF
tool v0.08.40.
Signed-off-by: Dave Gerlach <d-gerl...@ti.com>
Signed-off-by: Anand Gadiyar <gadi...@ti.com>
---
...33MTs.dtsi => k3-am64-sk-lp4-1600MTs.dtsi} | 371 +++++++++---------
arch/arm/dts/k3-am642-r5-sk.dts | 2 +-
2 files changed, 186 insertions(+), 187 deletions(-)
rename arch/arm/dts/{k3-am64-sk-lp4-1333MTs.dtsi =>
k3-am64-sk-lp4-1600MTs.dtsi} (91%)
diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi
similarity index 91%
rename from arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
rename to arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi
index dde5ab150d..f225c1f067 100644
--- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
+++ b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi
@@ -1,18 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated with the
- * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00
- * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time)
+ * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
+ * Wed Feb 02 2022 16:59:34 GMT-0600 (Central Standard Time)
* DDR Type: LPDDR4
- * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz
+ * F0 = 50MHz F1 = 800MHz F2 = 800MHz
* Density (per channel): 16Gb
* Number of Ranks: 1
-*/
+ */
#define DDRSS_PLL_FHS_CNT 6
-#define DDRSS_PLL_FREQUENCY_1 333350000
-#define DDRSS_PLL_FREQUENCY_2 333350000
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -25,14 +24,14 @@
#define DDRSS_CTL_8_DATA 0x000186A0
#define DDRSS_CTL_9_DATA 0x00000005
#define DDRSS_CTL_10_DATA 0x00000064
-#define DDRSS_CTL_11_DATA 0x000208D6
-#define DDRSS_CTL_12_DATA 0x00145856
+#define DDRSS_CTL_11_DATA 0x00027100
+#define DDRSS_CTL_12_DATA 0x00186A00
#define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000536
-#define DDRSS_CTL_15_DATA 0x000208D6
-#define DDRSS_CTL_16_DATA 0x00145856
+#define DDRSS_CTL_14_DATA 0x00000640
+#define DDRSS_CTL_15_DATA 0x00027100
+#define DDRSS_CTL_16_DATA 0x00186A00
#define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000536
+#define DDRSS_CTL_18_DATA 0x00000640
#define DDRSS_CTL_19_DATA 0x01010100
#define DDRSS_CTL_20_DATA 0x01010100
#define DDRSS_CTL_21_DATA 0x01000110
@@ -48,8 +47,8 @@
#define DDRSS_CTL_31_DATA 0x00000000
#define DDRSS_CTL_32_DATA 0x00000000
#define DDRSS_CTL_33_DATA 0x00000000
-#define DDRSS_CTL_34_DATA 0x02000010
-#define DDRSS_CTL_35_DATA 0x00001B1B
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00002020
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0000040C
@@ -62,64 +61,64 @@
#define DDRSS_CTL_45_DATA 0x00000700
#define DDRSS_CTL_46_DATA 0x09090004
#define DDRSS_CTL_47_DATA 0x00000203
-#define DDRSS_CTL_48_DATA 0x00290006
-#define DDRSS_CTL_49_DATA 0x0909001D
-#define DDRSS_CTL_50_DATA 0x0000150C
-#define DDRSS_CTL_51_DATA 0x00290006
-#define DDRSS_CTL_52_DATA 0x0909001D
-#define DDRSS_CTL_53_DATA 0x0900150C
+#define DDRSS_CTL_48_DATA 0x00320007
+#define DDRSS_CTL_49_DATA 0x09090023
+#define DDRSS_CTL_50_DATA 0x0000190F
+#define DDRSS_CTL_51_DATA 0x00320007
+#define DDRSS_CTL_52_DATA 0x09090023
+#define DDRSS_CTL_53_DATA 0x0900190F
#define DDRSS_CTL_54_DATA 0x000A0A09
#define DDRSS_CTL_55_DATA 0x040006DB
#define DDRSS_CTL_56_DATA 0x09092004
-#define DDRSS_CTL_57_DATA 0x00000A0A
-#define DDRSS_CTL_58_DATA 0x05005B68
-#define DDRSS_CTL_59_DATA 0x09092005
-#define DDRSS_CTL_60_DATA 0x00000A0A
-#define DDRSS_CTL_61_DATA 0x05005B68
-#define DDRSS_CTL_62_DATA 0x03042005
+#define DDRSS_CTL_57_DATA 0x00000C0A
+#define DDRSS_CTL_58_DATA 0x06006DB0
+#define DDRSS_CTL_59_DATA 0x09092006
+#define DDRSS_CTL_60_DATA 0x00000C0A
+#define DDRSS_CTL_61_DATA 0x06006DB0
+#define DDRSS_CTL_62_DATA 0x03042006
#define DDRSS_CTL_63_DATA 0x04050002
-#define DDRSS_CTL_64_DATA 0x0E0D0E0D
+#define DDRSS_CTL_64_DATA 0x100F100F
#define DDRSS_CTL_65_DATA 0x01010008
-#define DDRSS_CTL_66_DATA 0x041A1A07
-#define DDRSS_CTL_67_DATA 0x030E0E03
-#define DDRSS_CTL_68_DATA 0x00000E0E
+#define DDRSS_CTL_66_DATA 0x041F1F07
+#define DDRSS_CTL_67_DATA 0x03111103
+#define DDRSS_CTL_68_DATA 0x00001111
#define DDRSS_CTL_69_DATA 0x00000101
#define DDRSS_CTL_70_DATA 0x00000000
#define DDRSS_CTL_71_DATA 0x01000000
#define DDRSS_CTL_72_DATA 0x00130803
#define DDRSS_CTL_73_DATA 0x000000BB
-#define DDRSS_CTL_74_DATA 0x000000FE
-#define DDRSS_CTL_75_DATA 0x00000A20
-#define DDRSS_CTL_76_DATA 0x000000FE
-#define DDRSS_CTL_77_DATA 0x00000A20
+#define DDRSS_CTL_74_DATA 0x00000130
+#define DDRSS_CTL_75_DATA 0x00000C28
+#define DDRSS_CTL_76_DATA 0x00000130
+#define DDRSS_CTL_77_DATA 0x00000C28
#define DDRSS_CTL_78_DATA 0x00000005
#define DDRSS_CTL_79_DATA 0x0000000A
#define DDRSS_CTL_80_DATA 0x00000010
-#define DDRSS_CTL_81_DATA 0x0000007F
-#define DDRSS_CTL_82_DATA 0x0000013D
-#define DDRSS_CTL_83_DATA 0x0000007F
-#define DDRSS_CTL_84_DATA 0x0000013D
+#define DDRSS_CTL_81_DATA 0x00000098
+#define DDRSS_CTL_82_DATA 0x0000017E
+#define DDRSS_CTL_83_DATA 0x00000098
+#define DDRSS_CTL_84_DATA 0x0000017E
#define DDRSS_CTL_85_DATA 0x03004000
#define DDRSS_CTL_86_DATA 0x00001201
-#define DDRSS_CTL_87_DATA 0x00050005
-#define DDRSS_CTL_88_DATA 0x00000005
+#define DDRSS_CTL_87_DATA 0x00060005
+#define DDRSS_CTL_88_DATA 0x00000006
#define DDRSS_CTL_89_DATA 0x00000000
-#define DDRSS_CTL_90_DATA 0x05101008
+#define DDRSS_CTL_90_DATA 0x05121208
#define DDRSS_CTL_91_DATA 0x05030A05
-#define DDRSS_CTL_92_DATA 0x05030A05
-#define DDRSS_CTL_93_DATA 0x01030A05
+#define DDRSS_CTL_92_DATA 0x05030C06
+#define DDRSS_CTL_93_DATA 0x01030C06
#define DDRSS_CTL_94_DATA 0x02010201
#define DDRSS_CTL_95_DATA 0x00001401
-#define DDRSS_CTL_96_DATA 0x01030014
-#define DDRSS_CTL_97_DATA 0x01030103
-#define DDRSS_CTL_98_DATA 0x00000103
+#define DDRSS_CTL_96_DATA 0x01360014
+#define DDRSS_CTL_97_DATA 0x01360136
+#define DDRSS_CTL_98_DATA 0x00000136
#define DDRSS_CTL_99_DATA 0x00000000
#define DDRSS_CTL_100_DATA 0x05010303
-#define DDRSS_CTL_101_DATA 0x0A040505
-#define DDRSS_CTL_102_DATA 0x05050203
-#define DDRSS_CTL_103_DATA 0x030A0505
-#define DDRSS_CTL_104_DATA 0x05050502
-#define DDRSS_CTL_105_DATA 0x03030305
+#define DDRSS_CTL_101_DATA 0x0C040505
+#define DDRSS_CTL_102_DATA 0x06050203
+#define DDRSS_CTL_103_DATA 0x030C0605
+#define DDRSS_CTL_104_DATA 0x05060502
+#define DDRSS_CTL_105_DATA 0x03030306
#define DDRSS_CTL_106_DATA 0x03010000
#define DDRSS_CTL_107_DATA 0x00010000
#define DDRSS_CTL_108_DATA 0x00000000
@@ -140,20 +139,20 @@
#define DDRSS_CTL_123_DATA 0x00002EC0
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x0000051D
-#define DDRSS_CTL_126_DATA 0x00028800
-#define DDRSS_CTL_127_DATA 0x00028800
-#define DDRSS_CTL_128_DATA 0x00028800
-#define DDRSS_CTL_129_DATA 0x00028800
-#define DDRSS_CTL_130_DATA 0x00028800
+#define DDRSS_CTL_126_DATA 0x00030A00
+#define DDRSS_CTL_127_DATA 0x00030A00
+#define DDRSS_CTL_128_DATA 0x00030A00
+#define DDRSS_CTL_129_DATA 0x00030A00
+#define DDRSS_CTL_130_DATA 0x00030A00
#define DDRSS_CTL_131_DATA 0x00000000
-#define DDRSS_CTL_132_DATA 0x000046E0
-#define DDRSS_CTL_133_DATA 0x00028800
-#define DDRSS_CTL_134_DATA 0x00028800
-#define DDRSS_CTL_135_DATA 0x00028800
-#define DDRSS_CTL_136_DATA 0x00028800
-#define DDRSS_CTL_137_DATA 0x00028800
+#define DDRSS_CTL_132_DATA 0x00005518
+#define DDRSS_CTL_133_DATA 0x00030A00
+#define DDRSS_CTL_134_DATA 0x00030A00
+#define DDRSS_CTL_135_DATA 0x00030A00
+#define DDRSS_CTL_136_DATA 0x00030A00
+#define DDRSS_CTL_137_DATA 0x00030A00
#define DDRSS_CTL_138_DATA 0x00000000
-#define DDRSS_CTL_139_DATA 0x000046E0
+#define DDRSS_CTL_139_DATA 0x00005518
#define DDRSS_CTL_140_DATA 0x00000000
#define DDRSS_CTL_141_DATA 0x00000000
#define DDRSS_CTL_142_DATA 0x00000000
@@ -209,12 +208,12 @@
#define DDRSS_CTL_192_DATA 0x0005000A
#define DDRSS_CTL_193_DATA 0x0404000D
#define DDRSS_CTL_194_DATA 0x0000000D
-#define DDRSS_CTL_195_DATA 0x00430086
-#define DDRSS_CTL_196_DATA 0x050500A7
-#define DDRSS_CTL_197_DATA 0x000000A7
-#define DDRSS_CTL_198_DATA 0x00430086
-#define DDRSS_CTL_199_DATA 0x050500A7
-#define DDRSS_CTL_200_DATA 0x000000A7
+#define DDRSS_CTL_195_DATA 0x005000A0
+#define DDRSS_CTL_196_DATA 0x060600C8
+#define DDRSS_CTL_197_DATA 0x000000C8
+#define DDRSS_CTL_198_DATA 0x005000A0
+#define DDRSS_CTL_199_DATA 0x060600C8
+#define DDRSS_CTL_200_DATA 0x000000C8
#define DDRSS_CTL_201_DATA 0x00000000
#define DDRSS_CTL_202_DATA 0x00000000
#define DDRSS_CTL_203_DATA 0x00000000
@@ -239,11 +238,11 @@
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000031
-#define DDRSS_CTL_225_DATA 0x00000031
-#define DDRSS_CTL_226_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x000000B1
+#define DDRSS_CTL_226_DATA 0x000000B1
#define DDRSS_CTL_227_DATA 0x00000031
-#define DDRSS_CTL_228_DATA 0x00000031
-#define DDRSS_CTL_229_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
#define DDRSS_CTL_230_DATA 0x00000000
#define DDRSS_CTL_231_DATA 0x00000000
#define DDRSS_CTL_232_DATA 0x00000000
@@ -323,12 +322,12 @@
#define DDRSS_CTL_306_DATA 0x00400100
#define DDRSS_CTL_307_DATA 0x00080032
#define DDRSS_CTL_308_DATA 0x01000200
-#define DDRSS_CTL_309_DATA 0x029B0040
-#define DDRSS_CTL_310_DATA 0x00020014
+#define DDRSS_CTL_309_DATA 0x03200040
+#define DDRSS_CTL_310_DATA 0x00020018
#define DDRSS_CTL_311_DATA 0x00400100
-#define DDRSS_CTL_312_DATA 0x0014029B
+#define DDRSS_CTL_312_DATA 0x00180320
#define DDRSS_CTL_313_DATA 0x00030000
-#define DDRSS_CTL_314_DATA 0x00220022
+#define DDRSS_CTL_314_DATA 0x00280028
#define DDRSS_CTL_315_DATA 0x00000100
#define DDRSS_CTL_316_DATA 0x01010000
#define DDRSS_CTL_317_DATA 0x00000000
@@ -344,9 +343,9 @@
#define DDRSS_CTL_327_DATA 0x00000C01
#define DDRSS_CTL_328_DATA 0x01000100
#define DDRSS_CTL_329_DATA 0x00000000
-#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_330_DATA 0x00000000
#define DDRSS_CTL_331_DATA 0x01030303
-#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_332_DATA 0x00000001
#define DDRSS_CTL_333_DATA 0x00000000
#define DDRSS_CTL_334_DATA 0x00000000
#define DDRSS_CTL_335_DATA 0x00000000
@@ -390,14 +389,14 @@
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x01050503
#define DDRSS_CTL_375_DATA 0x05020201
-#define DDRSS_CTL_376_DATA 0x08080B0B
+#define DDRSS_CTL_376_DATA 0x08080C0C
#define DDRSS_CTL_377_DATA 0x00080308
-#define DDRSS_CTL_378_DATA 0x000C030E
-#define DDRSS_CTL_379_DATA 0x000C0310
-#define DDRSS_CTL_380_DATA 0x0C0C0810
+#define DDRSS_CTL_378_DATA 0x000B030E
+#define DDRSS_CTL_379_DATA 0x000B0310
+#define DDRSS_CTL_380_DATA 0x0B0B0810
#define DDRSS_CTL_381_DATA 0x01000000
-#define DDRSS_CTL_382_DATA 0x03010301
-#define DDRSS_CTL_383_DATA 0x04000101
+#define DDRSS_CTL_382_DATA 0x03020301
+#define DDRSS_CTL_383_DATA 0x04000102
#define DDRSS_CTL_384_DATA 0x1B000004
#define DDRSS_CTL_385_DATA 0x00000176
#define DDRSS_CTL_386_DATA 0x00000200
@@ -407,24 +406,24 @@
#define DDRSS_CTL_390_DATA 0x00000693
#define DDRSS_CTL_391_DATA 0x00000E9C
#define DDRSS_CTL_392_DATA 0x03050202
-#define DDRSS_CTL_393_DATA 0x00240201
-#define DDRSS_CTL_394_DATA 0x00001440
+#define DDRSS_CTL_393_DATA 0x00250201
+#define DDRSS_CTL_394_DATA 0x00001850
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
#define DDRSS_CTL_397_DATA 0x00000200
#define DDRSS_CTL_398_DATA 0x00000200
-#define DDRSS_CTL_399_DATA 0x00005B20
-#define DDRSS_CTL_400_DATA 0x0000CA80
-#define DDRSS_CTL_401_DATA 0x080D0402
-#define DDRSS_CTL_402_DATA 0x00240405
-#define DDRSS_CTL_403_DATA 0x00001440
+#define DDRSS_CTL_399_DATA 0x00006D68
+#define DDRSS_CTL_400_DATA 0x0000F320
+#define DDRSS_CTL_401_DATA 0x070D0402
+#define DDRSS_CTL_402_DATA 0x00250405
+#define DDRSS_CTL_403_DATA 0x00001850
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
-#define DDRSS_CTL_408_DATA 0x00005B20
-#define DDRSS_CTL_409_DATA 0x0000CA80
-#define DDRSS_CTL_410_DATA 0x080D0402
+#define DDRSS_CTL_408_DATA 0x00006D68
+#define DDRSS_CTL_409_DATA 0x0000F320
+#define DDRSS_CTL_410_DATA 0x070D0402
#define DDRSS_CTL_411_DATA 0x00000405
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
@@ -483,7 +482,7 @@
#define DDRSS_PI_43_DATA 0x00000000
#define DDRSS_PI_44_DATA 0x00000000
#define DDRSS_PI_45_DATA 0x00010100
-#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_46_DATA 0x00000015
#define DDRSS_PI_47_DATA 0x000007D0
#define DDRSS_PI_48_DATA 0x00000300
#define DDRSS_PI_49_DATA 0x00000000
@@ -602,8 +601,8 @@
#define DDRSS_PI_162_DATA 0x00000000
#define DDRSS_PI_163_DATA 0x00000000
#define DDRSS_PI_164_DATA 0x00000800
-#define DDRSS_PI_165_DATA 0x00640064
-#define DDRSS_PI_166_DATA 0x000E0E01
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00101001
#define DDRSS_PI_167_DATA 0x00000034
#define DDRSS_PI_168_DATA 0x00000042
#define DDRSS_PI_169_DATA 0x00020042
@@ -614,84 +613,84 @@
#define DDRSS_PI_174_DATA 0x001C0000
#define DDRSS_PI_175_DATA 0x00000013
#define DDRSS_PI_176_DATA 0x000000BB
-#define DDRSS_PI_177_DATA 0x000000FE
-#define DDRSS_PI_178_DATA 0x00000A20
-#define DDRSS_PI_179_DATA 0x000000FE
-#define DDRSS_PI_180_DATA 0x04000A20
+#define DDRSS_PI_177_DATA 0x00000130
+#define DDRSS_PI_178_DATA 0x00000C28
+#define DDRSS_PI_179_DATA 0x00000130
+#define DDRSS_PI_180_DATA 0x04000C28
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001501
-#define DDRSS_PI_183_DATA 0x001B001B
+#define DDRSS_PI_183_DATA 0x001D001D
#define DDRSS_PI_184_DATA 0x01000100
#define DDRSS_PI_185_DATA 0x00000100
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05050503
-#define DDRSS_PI_188_DATA 0x01010B0B
+#define DDRSS_PI_188_DATA 0x01010C0C
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x000C0C0A
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x04000000
-#define DDRSS_PI_194_DATA 0x04020909
+#define DDRSS_PI_194_DATA 0x04020808
#define DDRSS_PI_195_DATA 0x04040204
#define DDRSS_PI_196_DATA 0x00090031
-#define DDRSS_PI_197_DATA 0x000F0037
-#define DDRSS_PI_198_DATA 0x000F0037
+#define DDRSS_PI_197_DATA 0x00110039
+#define DDRSS_PI_198_DATA 0x00110039
#define DDRSS_PI_199_DATA 0x01010101
-#define DDRSS_PI_200_DATA 0x0001000D
-#define DDRSS_PI_201_DATA 0x000100A7
-#define DDRSS_PI_202_DATA 0x010000A7
+#define DDRSS_PI_200_DATA 0x0002000D
+#define DDRSS_PI_201_DATA 0x000200C8
+#define DDRSS_PI_202_DATA 0x010000C8
#define DDRSS_PI_203_DATA 0x000E000E
-#define DDRSS_PI_204_DATA 0x00A80100
-#define DDRSS_PI_205_DATA 0x010000A8
-#define DDRSS_PI_206_DATA 0x00A800A8
+#define DDRSS_PI_204_DATA 0x00C90100
+#define DDRSS_PI_205_DATA 0x010000C9
+#define DDRSS_PI_206_DATA 0x00C900C9
#define DDRSS_PI_207_DATA 0x32103200
#define DDRSS_PI_208_DATA 0x01013210
#define DDRSS_PI_209_DATA 0x0A070601
-#define DDRSS_PI_210_DATA 0x0B08070D
-#define DDRSS_PI_211_DATA 0x0B08070D
+#define DDRSS_PI_210_DATA 0x0D09070D
+#define DDRSS_PI_211_DATA 0x0D09070D
#define DDRSS_PI_212_DATA 0x000C000D
#define DDRSS_PI_213_DATA 0x00001000
#define DDRSS_PI_214_DATA 0x00000C00
#define DDRSS_PI_215_DATA 0x00001000
#define DDRSS_PI_216_DATA 0x00000C00
#define DDRSS_PI_217_DATA 0x02001000
-#define DDRSS_PI_218_DATA 0x0015000D
-#define DDRSS_PI_219_DATA 0x001500A7
-#define DDRSS_PI_220_DATA 0x000000A7
+#define DDRSS_PI_218_DATA 0x0016000D
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x000000C8
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
#define DDRSS_PI_223_DATA 0x06000101
#define DDRSS_PI_224_DATA 0x001D0204
-#define DDRSS_PI_225_DATA 0x32120059
+#define DDRSS_PI_225_DATA 0x32120058
#define DDRSS_PI_226_DATA 0x05000101
-#define DDRSS_PI_227_DATA 0x001D0409
-#define DDRSS_PI_228_DATA 0x32120059
+#define DDRSS_PI_227_DATA 0x001D0408
+#define DDRSS_PI_228_DATA 0x32120058
#define DDRSS_PI_229_DATA 0x05000101
-#define DDRSS_PI_230_DATA 0x00000409
+#define DDRSS_PI_230_DATA 0x00000408
#define DDRSS_PI_231_DATA 0x05030900
#define DDRSS_PI_232_DATA 0x00040900
#define DDRSS_PI_233_DATA 0x0000062B
#define DDRSS_PI_234_DATA 0x20010004
#define DDRSS_PI_235_DATA 0x0A0A0A03
-#define DDRSS_PI_236_DATA 0x0E090000
-#define DDRSS_PI_237_DATA 0x0E09000D
-#define DDRSS_PI_238_DATA 0x00005244
-#define DDRSS_PI_239_DATA 0x2003001D
-#define DDRSS_PI_240_DATA 0x0A0A0A0A
-#define DDRSS_PI_241_DATA 0x0E090000
-#define DDRSS_PI_242_DATA 0x0E09000D
-#define DDRSS_PI_243_DATA 0x00005244
-#define DDRSS_PI_244_DATA 0x2003001D
-#define DDRSS_PI_245_DATA 0x0A0A0A0A
+#define DDRSS_PI_236_DATA 0x11090000
+#define DDRSS_PI_237_DATA 0x1009000F
+#define DDRSS_PI_238_DATA 0x000062B8
+#define DDRSS_PI_239_DATA 0x20030023
+#define DDRSS_PI_240_DATA 0x0C0A0C0C
+#define DDRSS_PI_241_DATA 0x11090000
+#define DDRSS_PI_242_DATA 0x1009000F
+#define DDRSS_PI_243_DATA 0x000062B8
+#define DDRSS_PI_244_DATA 0x20030023
+#define DDRSS_PI_245_DATA 0x0C0A0C0C
#define DDRSS_PI_246_DATA 0x00000000
#define DDRSS_PI_247_DATA 0x00000176
#define DDRSS_PI_248_DATA 0x00000E9C
-#define DDRSS_PI_249_DATA 0x00001440
-#define DDRSS_PI_250_DATA 0x0000CA80
-#define DDRSS_PI_251_DATA 0x00001440
-#define DDRSS_PI_252_DATA 0x0000CA80
-#define DDRSS_PI_253_DATA 0x01030014
-#define DDRSS_PI_254_DATA 0x03030103
+#define DDRSS_PI_249_DATA 0x00001850
+#define DDRSS_PI_250_DATA 0x0000F320
+#define DDRSS_PI_251_DATA 0x00001850
+#define DDRSS_PI_252_DATA 0x0000F320
+#define DDRSS_PI_253_DATA 0x01360014
+#define DDRSS_PI_254_DATA 0x03030136
#define DDRSS_PI_255_DATA 0x00000003
#define DDRSS_PI_256_DATA 0x00000000
#define DDRSS_PI_257_DATA 0x05030503
@@ -701,23 +700,23 @@
#define DDRSS_PI_261_DATA 0x00000005
#define DDRSS_PI_262_DATA 0x00000064
#define DDRSS_PI_263_DATA 0x00000014
-#define DDRSS_PI_264_DATA 0x000208D6
+#define DDRSS_PI_264_DATA 0x00027100
#define DDRSS_PI_265_DATA 0x000186A0
#define DDRSS_PI_266_DATA 0x00000005
-#define DDRSS_PI_267_DATA 0x00000536
-#define DDRSS_PI_268_DATA 0x00000103
-#define DDRSS_PI_269_DATA 0x000208D6
+#define DDRSS_PI_267_DATA 0x00000640
+#define DDRSS_PI_268_DATA 0x00000136
+#define DDRSS_PI_269_DATA 0x00027100
#define DDRSS_PI_270_DATA 0x000186A0
#define DDRSS_PI_271_DATA 0x00000005
-#define DDRSS_PI_272_DATA 0x00000536
-#define DDRSS_PI_273_DATA 0x01000103
+#define DDRSS_PI_272_DATA 0x00000640
+#define DDRSS_PI_273_DATA 0x01000136
#define DDRSS_PI_274_DATA 0x00320040
#define DDRSS_PI_275_DATA 0x00010008
-#define DDRSS_PI_276_DATA 0x029B0040
-#define DDRSS_PI_277_DATA 0x00010014
-#define DDRSS_PI_278_DATA 0x029B0040
-#define DDRSS_PI_279_DATA 0x00000314
-#define DDRSS_PI_280_DATA 0x00280021
+#define DDRSS_PI_276_DATA 0x03200040
+#define DDRSS_PI_277_DATA 0x00010018
+#define DDRSS_PI_278_DATA 0x03200040
+#define DDRSS_PI_279_DATA 0x00000318
+#define DDRSS_PI_280_DATA 0x00280028
#define DDRSS_PI_281_DATA 0x03040404
#define DDRSS_PI_282_DATA 0x00000303
#define DDRSS_PI_283_DATA 0x02020101
@@ -745,7 +744,7 @@
#define DDRSS_PI_305_DATA 0x00000000
#define DDRSS_PI_306_DATA 0x00000024
#define DDRSS_PI_307_DATA 0x00000012
-#define DDRSS_PI_308_DATA 0x00000031
+#define DDRSS_PI_308_DATA 0x000000B1
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
#define DDRSS_PI_311_DATA 0x46000000
@@ -753,7 +752,7 @@
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
#define DDRSS_PI_315_DATA 0x00000012
-#define DDRSS_PI_316_DATA 0x00000031
+#define DDRSS_PI_316_DATA 0x000000B1
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
#define DDRSS_PI_319_DATA 0x46000000
@@ -769,7 +768,7 @@
#define DDRSS_PI_329_DATA 0x00000000
#define DDRSS_PI_330_DATA 0x00000024
#define DDRSS_PI_331_DATA 0x00000012
-#define DDRSS_PI_332_DATA 0x00000031
+#define DDRSS_PI_332_DATA 0x000000B1
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
#define DDRSS_PI_335_DATA 0x46000000
@@ -777,7 +776,7 @@
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
#define DDRSS_PI_339_DATA 0x00000012
-#define DDRSS_PI_340_DATA 0x00000031
+#define DDRSS_PI_340_DATA 0x000000B1
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
#define DDRSS_PI_343_DATA 0x46000000
@@ -869,29 +868,29 @@
#define DDRSS_PHY_84_DATA 0x00100010
#define DDRSS_PHY_85_DATA 0x00100010
#define DDRSS_PHY_86_DATA 0x00100010
-#define DDRSS_PHY_87_DATA 0x02000010
+#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
#define DDRSS_PHY_90_DATA 0x07AB0340
#define DDRSS_PHY_91_DATA 0x0000C0C0
-#define DDRSS_PHY_92_DATA 0x03040000
-#define DDRSS_PHY_93_DATA 0x00000403
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
#define DDRSS_PHY_94_DATA 0x42100010
#define DDRSS_PHY_95_DATA 0x010C053E
-#define DDRSS_PHY_96_DATA 0x000F0C1A
+#define DDRSS_PHY_96_DATA 0x000F0C1D
#define DDRSS_PHY_97_DATA 0x01000140
-#define DDRSS_PHY_98_DATA 0x00660120
+#define DDRSS_PHY_98_DATA 0x007A0120
#define DDRSS_PHY_99_DATA 0x00000C00
-#define DDRSS_PHY_100_DATA 0x000001AA
+#define DDRSS_PHY_100_DATA 0x000001CC
#define DDRSS_PHY_101_DATA 0x20100200
-#define DDRSS_PHY_102_DATA 0x00000004
+#define DDRSS_PHY_102_DATA 0x00000005
#define DDRSS_PHY_103_DATA 0x76543210
#define DDRSS_PHY_104_DATA 0x00000008
-#define DDRSS_PHY_105_DATA 0x032A032A
-#define DDRSS_PHY_106_DATA 0x032A032A
-#define DDRSS_PHY_107_DATA 0x032A032A
-#define DDRSS_PHY_108_DATA 0x032A032A
-#define DDRSS_PHY_109_DATA 0x0000032A
+#define DDRSS_PHY_105_DATA 0x034C034C
+#define DDRSS_PHY_106_DATA 0x034C034C
+#define DDRSS_PHY_107_DATA 0x034C034C
+#define DDRSS_PHY_108_DATA 0x034C034C
+#define DDRSS_PHY_109_DATA 0x0000034C
#define DDRSS_PHY_110_DATA 0x00008000
#define DDRSS_PHY_111_DATA 0x00800080
#define DDRSS_PHY_112_DATA 0x00800080
@@ -901,7 +900,7 @@
#define DDRSS_PHY_116_DATA 0x00800080
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
-#define DDRSS_PHY_119_DATA 0x01190080
+#define DDRSS_PHY_119_DATA 0x01800080
#define DDRSS_PHY_120_DATA 0x01A00001
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
@@ -1125,29 +1124,29 @@
#define DDRSS_PHY_340_DATA 0x00100010
#define DDRSS_PHY_341_DATA 0x00100010
#define DDRSS_PHY_342_DATA 0x00100010
-#define DDRSS_PHY_343_DATA 0x02000010
+#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
#define DDRSS_PHY_346_DATA 0x07AB0340
#define DDRSS_PHY_347_DATA 0x0000C0C0
-#define DDRSS_PHY_348_DATA 0x03040000
-#define DDRSS_PHY_349_DATA 0x00000403
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
#define DDRSS_PHY_350_DATA 0x42100010
#define DDRSS_PHY_351_DATA 0x010C053E
-#define DDRSS_PHY_352_DATA 0x000F0C1A
+#define DDRSS_PHY_352_DATA 0x000F0C1D
#define DDRSS_PHY_353_DATA 0x01000140
-#define DDRSS_PHY_354_DATA 0x00660120
+#define DDRSS_PHY_354_DATA 0x007A0120
#define DDRSS_PHY_355_DATA 0x00000C00
-#define DDRSS_PHY_356_DATA 0x000001AA
+#define DDRSS_PHY_356_DATA 0x000001CC
#define DDRSS_PHY_357_DATA 0x20100200
-#define DDRSS_PHY_358_DATA 0x00000004
+#define DDRSS_PHY_358_DATA 0x00000005
#define DDRSS_PHY_359_DATA 0x76543210
#define DDRSS_PHY_360_DATA 0x00000008
-#define DDRSS_PHY_361_DATA 0x032A032A
-#define DDRSS_PHY_362_DATA 0x032A032A
-#define DDRSS_PHY_363_DATA 0x032A032A
-#define DDRSS_PHY_364_DATA 0x032A032A
-#define DDRSS_PHY_365_DATA 0x0000032A
+#define DDRSS_PHY_361_DATA 0x034C034C
+#define DDRSS_PHY_362_DATA 0x034C034C
+#define DDRSS_PHY_363_DATA 0x034C034C
+#define DDRSS_PHY_364_DATA 0x034C034C
+#define DDRSS_PHY_365_DATA 0x0000034C
#define DDRSS_PHY_366_DATA 0x00008000
#define DDRSS_PHY_367_DATA 0x00800080
#define DDRSS_PHY_368_DATA 0x00800080
@@ -1157,7 +1156,7 @@
#define DDRSS_PHY_372_DATA 0x00800080
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
-#define DDRSS_PHY_375_DATA 0x01190080
+#define DDRSS_PHY_375_DATA 0x01800080
#define DDRSS_PHY_376_DATA 0x01A00001
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
@@ -1326,7 +1325,7 @@
#define DDRSS_PHY_541_DATA 0x003F0000
#define DDRSS_PHY_542_DATA 0x000F013F
#define DDRSS_PHY_543_DATA 0x0000000F
-#define DDRSS_PHY_544_DATA 0x000002CC
+#define DDRSS_PHY_544_DATA 0x020002CC
#define DDRSS_PHY_545_DATA 0x00030000
#define DDRSS_PHY_546_DATA 0x00000300
#define DDRSS_PHY_547_DATA 0x00000300
@@ -1582,7 +1581,7 @@
#define DDRSS_PHY_797_DATA 0x00000000
#define DDRSS_PHY_798_DATA 0x000F0000
#define DDRSS_PHY_799_DATA 0x0000000F
-#define DDRSS_PHY_800_DATA 0x000002CC
+#define DDRSS_PHY_800_DATA 0x020002CC
#define DDRSS_PHY_801_DATA 0x00030000
#define DDRSS_PHY_802_DATA 0x00000300
#define DDRSS_PHY_803_DATA 0x00000300
@@ -1838,7 +1837,7 @@
#define DDRSS_PHY_1053_DATA 0x10000000
#define DDRSS_PHY_1054_DATA 0x000F0000
#define DDRSS_PHY_1055_DATA 0x0000000F
-#define DDRSS_PHY_1056_DATA 0x000002CC
+#define DDRSS_PHY_1056_DATA 0x020002CC
#define DDRSS_PHY_1057_DATA 0x00030000
#define DDRSS_PHY_1058_DATA 0x00000300
#define DDRSS_PHY_1059_DATA 0x00000300
@@ -2116,7 +2115,7 @@
#define DDRSS_PHY_1331_DATA 0x00004410
#define DDRSS_PHY_1332_DATA 0x00000000
#define DDRSS_PHY_1333_DATA 0x00000076
-#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1334_DATA 0x00000400
#define DDRSS_PHY_1335_DATA 0x00000008
#define DDRSS_PHY_1336_DATA 0x00000000
#define DDRSS_PHY_1337_DATA 0x00000000
@@ -2154,7 +2153,7 @@
#define DDRSS_PHY_1369_DATA 0x00000000
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
-#define DDRSS_PHY_1372_DATA 0x00000002
+#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142
#define DDRSS_PHY_1375_DATA 0x03020000
@@ -2187,4 +2186,4 @@
#define DDRSS_PHY_1402_DATA 0x019900E0
#define DDRSS_PHY_1403_DATA 0x00018011
#define DDRSS_PHY_1404_DATA 0x0089FF00
-#define DDRSS_PHY_1405_DATA 0x20040001
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index cf3ba0e209..97f44e220a 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -9,7 +9,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
-#include "k3-am64-sk-lp4-1333MTs.dtsi"
+#include "k3-am64-sk-lp4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
/ {
--
2.34.1
