[PATCH v1 6/6] riscv: dts: fix the mpfs's reference clock frequency

[Conor Dooley]

The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.

Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
Signed-off-by: Conor Dooley <conor.doo...@microchip.com>
---
 arch/riscv/dts/microchip-mpfs-icicle-kit.dts |  4 ++++
 arch/riscv/dts/microchip-mpfs.dtsi           | 14 ++++++--------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts 
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index e1fbedc507..7d87b181db 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -53,6 +53,10 @@
        };
 };
 
+&refclk {
+       clock-frequency = <125000000>;
+};
+
 &uart1 {
        status = "okay";
 };
diff --git a/arch/riscv/dts/microchip-mpfs.dtsi 
b/arch/riscv/dts/microchip-mpfs.dtsi
index 4f449a3a93..891dd0918b 100644
--- a/arch/riscv/dts/microchip-mpfs.dtsi
+++ b/arch/riscv/dts/microchip-mpfs.dtsi
@@ -170,6 +170,11 @@
                };
        };
 
+       refclk: refclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+       };
+
        soc {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -225,16 +230,9 @@
                                        &cpu4_intc HART_INT_M_EXT &cpu4_intc 
HART_INT_S_EXT>;
                };
 
-               refclk: refclk {
-                       compatible = "fixed-clock";
-                       #clock-cells = <0>;
-                       clock-frequency = <600000000>;
-                       clock-output-names = "msspllclk";
-               };
-
                clkcfg: clkcfg@20002000 {
                        compatible = "microchip,mpfs-clkcfg";
-                       reg = <0x0 0x20002000 0x0 0x1000>;
+                       reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 
0x1000>;
                        reg-names = "mss_sysreg";
                        clocks = <&refclk>;
                        #clock-cells = <1>;
-- 
2.38.0