Add MV88E61XX DSA support:
 - update dt to provide internal MDIO bus and port handles.
   U-Boot requires a more restrictive subset of the dt bindings
   required by Linux for the sake of simplifying code
 - update defconfig to remove old driver and enable new one
 - replace mv88e61xx_hw_reset weak override with board_phy_config support
   for register configuration that is outside the scope of the DSA driver

Signed-off-by: Tim Harvey <thar...@gateworks.com>
Reviewed-by: Fabio Estevam <feste...@denx.de>
Reviewed-by: Vladimir Oltean <vladimir.olt...@nxp.com>
---
v8:
 - added phy-mode = "internal" to phy ports
v7:
 - added Vladimir's rb tag
v6:
 - update commit message
 - squash accidently change to mv88e6xxx driver into previous patch
 - remove unused label for cpu port
v5:
 - fix typo in defconfig s/MV88E61XX/MV88E6XXX
 - added Fabio's rb tag
v4:
 - use standard Linux internal MDIO dt structure
 - use PHY_FIXED_ID define
v3:
 - move mdio's mdio@0 subnode
v2: no changes
---
 arch/arm/dts/imx6qdl-gw5904.dtsi        | 36 +++++++++++++++++-
 board/gateworks/gw_ventana/gw_ventana.c | 50 +++++++++----------------
 configs/gwventana_gw5904_defconfig      |  7 ++--
 3 files changed, 56 insertions(+), 37 deletions(-)

diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi
index 612b6e068e28..ea54922f15f8 100644
--- a/arch/arm/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5904.dtsi
@@ -212,6 +212,27 @@
                        compatible = "marvell,mv88e6085";
                        reg = <0>;
 
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               sw_phy0: ethernet-phy@0 {
+                                       reg = <0x0>;
+                               };
+
+                               sw_phy1: ethernet-phy@1 {
+                                       reg = <0x1>;
+                               };
+
+                               sw_phy2: ethernet-phy@2 {
+                                       reg = <0x2>;
+                               };
+
+                               sw_phy3: ethernet-phy@3 {
+                                       reg = <0x3>;
+                               };
+                       };
+
                        ports {
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -219,27 +240,40 @@
                                port@0 {
                                        reg = <0>;
                                        label = "lan4";
+                                       phy-handle = <&sw_phy0>;
+                                       phy-mode = "internal";
                                };
 
                                port@1 {
                                        reg = <1>;
                                        label = "lan3";
+                                       phy-handle = <&sw_phy1>;
+                                       phy-mode = "internal";
                                };
 
                                port@2 {
                                        reg = <2>;
                                        label = "lan2";
+                                       phy-handle = <&sw_phy2>;
+                                       phy-mode = "internal";
                                };
 
                                port@3 {
                                        reg = <3>;
                                        label = "lan1";
+                                       phy-handle = <&sw_phy3>;
+                                       phy-mode = "internal";
                                };
 
                                port@5 {
                                        reg = <5>;
-                                       label = "cpu";
                                        ethernet = <&fec>;
+                                       phy-mode = "rgmii-id";
+
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
                                };
                        };
                };
diff --git a/board/gateworks/gw_ventana/gw_ventana.c 
b/board/gateworks/gw_ventana/gw_ventana.c
index 0ecfd98c2261..683def7e9f71 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -83,44 +83,30 @@ int board_phy_config(struct phy_device *phydev)
                break;
        }
 
+       /* Fixed PHY: for GW5904/GW5909 this is Marvell 88E6176 GbE Switch */
+       if (phydev->phy_id == PHY_FIXED_ID &&
+           (board_type == GW5904 || board_type == GW5909)) {
+               struct mii_dev *bus = miiphy_get_dev_by_name("mdio");
+
+               puts("MV88E61XX ");
+               /* GPIO[0] output CLK125 for RGMII_REFCLK */
+               bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x62 << 8) | 0xfe);
+               bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x68 << 8) | 7);
+
+               /* Port 0-3 LED configuration: Table 80/82 */
+               /* LED configuration: 7:4-green (8=Activity)  3:0 amber 
(8=Link) */
+               bus->write(bus, 0x10, 0, 0x16, 0x8088);
+               bus->write(bus, 0x11, 0, 0x16, 0x8088);
+               bus->write(bus, 0x12, 0, 0x16, 0x8088);
+               bus->write(bus, 0x13, 0, 0x16, 0x8088);
+       }
+
        if (phydev->drv->config)
                phydev->drv->config(phydev);
 
        return 0;
 }
 
-#ifdef CONFIG_MV88E61XX_SWITCH
-int mv88e61xx_hw_reset(struct phy_device *phydev)
-{
-       struct mii_dev *bus = phydev->bus;
-
-       /* GPIO[0] output, CLK125 */
-       debug("enabling RGMII_REFCLK\n");
-       bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
-                  0x1a /*MV_SCRATCH_MISC*/,
-                  (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
-       bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
-                  0x1a /*MV_SCRATCH_MISC*/,
-                  (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
-
-       /* RGMII delay - Physical Control register bit[15:14] */
-       debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
-       /* forced 1000mbps full-duplex link */
-       bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
-       phydev->autoneg = AUTONEG_DISABLE;
-       phydev->speed = SPEED_1000;
-       phydev->duplex = DUPLEX_FULL;
-
-       /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
-       bus->write(bus, 0x10, 0, 0x16, 0x8088);
-       bus->write(bus, 0x11, 0, 0x16, 0x8088);
-       bus->write(bus, 0x12, 0, 0x16, 0x8088);
-       bus->write(bus, 0x13, 0, 0x16, 0x8088);
-
-       return 0;
-}
-#endif // CONFIG_MV88E61XX_SWITCH
-
 #if defined(CONFIG_VIDEO_IPUV3)
 static void enable_hdmi(struct display_info_t const *dev)
 {
diff --git a/configs/gwventana_gw5904_defconfig 
b/configs/gwventana_gw5904_defconfig
index a5b31514ff12..e2cb449b7636 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -108,13 +108,12 @@ CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
-CONFIG_MV88E61XX_SWITCH=y
-CONFIG_MV88E61XX_CPU_PORT=5
-CONFIG_MV88E61XX_PHY_PORTS=0xf
-CONFIG_MV88E61XX_FIXED_PORTS=0x0
+CONFIG_PHY_FIXED=y
 CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
 CONFIG_E1000=y
 CONFIG_FEC_MXC=y
+CONFIG_MV88E6XXX=y
 CONFIG_MII=y
 CONFIG_PCI=y
 CONFIG_PCIE_IMX=y
-- 
2.25.1

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