Am Do., 3. Nov. 2022 um 18:24 Uhr schrieb Tom Rini <tr...@konsulko.com>: > > On Thu, Nov 03, 2022 at 12:27:39AM -0500, Nishanth Menon wrote: > > On 13:15-20221026, Christian Gmeiner wrote: > > > Add the needed bus mappings for the two main RTI memory ranges and > > > the required device tree nodes in the main domain. > > > > > > Same as kernel commit 6dd8457dc20693e2ba9054c171499b22664fd4e7 > > > > > > Signed-off-by: Christian Gmeiner <christian.gmei...@gmail.com> > > > --- > > > arch/arm/dts/k3-am64-main.dtsi | 18 ++++++++++++++++++ > > > arch/arm/dts/k3-am64.dtsi | 2 ++ > > > 2 files changed, 20 insertions(+) > > > > > > diff --git a/arch/arm/dts/k3-am64-main.dtsi > > > b/arch/arm/dts/k3-am64-main.dtsi > > > index 02c3fdf9cc..57b0f53ac9 100644 > > > --- a/arch/arm/dts/k3-am64-main.dtsi > > > +++ b/arch/arm/dts/k3-am64-main.dtsi > > > @@ -859,4 +859,22 @@ > > > clock-names = "fck"; > > > max-functions = /bits/ 8 <1>; > > > }; > > > + > > > + main_rti0: watchdog@e000000 { > > > + compatible = "ti,j7-rti-wdt"; > > > + reg = <0x00 0xe000000 0x00 0x100>; > > > + clocks = <&k3_clks 125 0>; > > > + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; > > > + assigned-clocks = <&k3_clks 125 0>; > > > + assigned-clock-parents = <&k3_clks 125 2>; > > > + }; > > > + > > > + main_rti1: watchdog@e010000 { > > > + compatible = "ti,j7-rti-wdt"; > > > + reg = <0x00 0xe010000 0x00 0x100>; > > > + clocks = <&k3_clks 126 0>; > > > + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; > > > + assigned-clocks = <&k3_clks 126 0>; > > > + assigned-clock-parents = <&k3_clks 126 2>; > > > + }; > > > }; > > > diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi > > > index 7aa94d5a6e..053e7f42e9 100644 > > > --- a/arch/arm/dts/k3-am64.dtsi > > > +++ b/arch/arm/dts/k3-am64.dtsi > > > @@ -70,6 +70,8 @@ > > > <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, > > > /* First peripheral window */ > > > <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, > > > /* Main CPSW */ > > > <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, > > > /* PCIE_CORE */ > > > + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, > > > /* Main RTI0 */ > > > + <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, > > > /* Main RTI1 */ > > > <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, > > > /* Second peripheral window */ > > > <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, > > > /* Third peripheral window */ > > > <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, > > > /* ICSSG0/1 */ > > > -- > > > 2.37.3 > > > > > As I responded to > > https://lore.kernel.org/u-boot/20221103052101.l77rsp4siutbe72n@scientist/ > > as well.. > > > > I think we need to sync upstream kernel dts back into u-boot -> we will end > > up > > having more of these cherry-pick cases otherwise. > > Sorry, I had this queued up to merge and missed this email. How would > you like to proceed?
I want to see this change in the next U-Boot version. So let's drop my change here and hope TI mangeses to come up with the kernel -> U-Boot dts sync patch soon. -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy