On 11/21/22 09:50, Gary Bisson wrote: > Hi, > > On Fri, Nov 18, 2022 at 10:36:58AM -0500, Sean Anderson wrote: >> On 11/18/22 07:13, Gary Bisson wrote: >> > This reverts commit 62649165cb02ab95b57360bb362886935f524f26. >> > >> > The patch decreased the write performance quite a bit. >> > Here is an example on an i.MX 8M Quad platform. >> > - Before the revert: >> > Sending sparse 'vendor' 1/2 (516436 KB) OKAY [ 5.113s] >> > Writing 'vendor' OKAY [128.335s] >> > Sending sparse 'vendor' 2/2 (76100 KB) OKAY [ 0.802s] >> > Writing 'vendor' OKAY [ 27.902s] >> > - After the revert: >> > Sending sparse 'vendor' 1/2 (516436 KB) OKAY [ 5.310s] >> > Writing 'vendor' OKAY [ 18.041s] >> > Sending sparse 'vendor' 2/2 (76100 KB) OKAY [ 1.244s] >> > Writing 'vendor' OKAY [ 2.663s] >> > >> > Considering that the patch only moves buffer around to avoid a warning >> > message about misaligned buffers, let's keep the best performances. >> >> So what is the point of this warning? > > Well the warning does say something true that the cache operation is not > aligned. Better ask Simon as he's the one who changed the print from a > debug to warn_non_spl one: > bcc53bf0958 arm: Show cache warnings in U-Boot proper only > > BTW, in my case I couldn't see the misaligned messages, yet I saw the > performance hit described above.
Maybe it is better to keep this as a Kconfig? Some arches may support unaligned access but others may not. I wonder if we have something like this already. --Seam