From: Tien Fong Chee <tien.fong.c...@intel.com>

Update N5X existing firewall and secure register settings in source codes to
device tree.

Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon....@intel.com>
---
 arch/arm/dts/socfpga_n5x-u-boot.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi 
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
index 98cbd4c808..c25d99366a 100644
--- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -132,6 +132,8 @@
 &spi1 {
        clocks = <&clkmgr N5X_L4_MAIN_CLK>;
 
+};
+
 &socfpga_secreg {
        soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
                reg = <0xf8020000 0x0000001c>;
-- 
2.26.2

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