In case U-Boot is a PSCI provider, enable GICv3 support as this
is necessary to bring up secondary cores.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessan...@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-...@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul....@linaro.org>
Cc: Adam Ford <aford...@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainik...@toradex.com>
Cc: Fabio Estevam <feste...@gmail.com>
Cc: Manoj Sai <abbaraju.manoj...@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswi...@toradex.com>
Cc: Michael Trimarchi <mich...@amarulasolutions.com>
Cc: Peng Fan <peng....@nxp.com>
Cc: Ricardo Salveti <rica...@foundries.io>
Cc: Simon Glass <s...@chromium.org>
Cc: Stefano Babic <sba...@denx.de>
Cc: Tim Harvey <thar...@gateworks.com>
Cc: Ye Li <ye...@nxp.com>
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 3 +++
arch/arm/mach-imx/imx8m/Kconfig | 1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 20f4699a12b..cfd5479cd73 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -81,6 +81,9 @@
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+#define GICD_BASE 0x38800000
+#define GICR_BASE 0x38880000
+
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 3313ea38832..9e957e2de57 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMX8M
config IMX8M
bool
+ select GICV3 if ARMV8_PSCI
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
select ARMV8_CRYPTO
--
2.35.1
