On 1/19/23 01:18, David Abdurachmanov wrote:
On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
<yanhong.w...@starfivetech.com> wrote:

Add initial device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.w...@starfivetech.com>
---
  arch/riscv/dts/jh7110.dtsi | 497 +++++++++++++++++++++++++++++++++++++
  1 file changed, 497 insertions(+)
  create mode 100644 arch/riscv/dts/jh7110.dtsi

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
new file mode 100644
index 0000000000..49d34b85af
--- /dev/null
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -0,0 +1,497 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <ker...@esmil.dk>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/starfive-jh7110.h>
+#include <dt-bindings/reset/starfive-jh7110.h>
+
+/ {
+       compatible = "starfive,jh7110";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               S76_0: cpu@0 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <0>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <8192>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <16384>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imacu";
+                       tlb-split;
+                       status = "disabled";
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_1: cpu@1 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <1>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdcbsu";
+                       tlb-split;
+
+                       cpu1_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_2: cpu@2 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <2>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdcbsu";
+                       tlb-split;
+
+                       cpu2_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_3: cpu@3 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <3>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdcbsu";
+                       tlb-split;
+
+                       cpu3_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_4: cpu@4 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <4>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdcbsu";

Looking at SiFive U74 manuals, shouldn't this be RV64GC_Zba_Zbb_Sscofpmf?
U74 only supports Zba and Zbb bit manip extensions.
This is from the 21G3.02.00 release manual.

Looking more, S76 core is listed in the manual as supporting up to:
RV64IMAC_Zicsr_Zifencei_Zba_Zbb_Sscofpmf.

I almost forgot about _Zicsr_Zifencei (which are part of G). Shouldn't
those be listed too in riscv,isa?

AFAIK we don't support Z/X in U-Boot.

--Sean

+                       tlb-split;
+
+                       cpu4_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&S76_0>;
+                               };
+
+                               core1 {
+                                       cpu = <&U74_1>;
+                               };
+
+                               core2 {
+                                       cpu = <&U74_2>;
+                               };
+
+                               core3 {
+                                       cpu = <&U74_3>;
+                               };
+
+                               core4 {
+                                       cpu = <&U74_4>;
+                               };
+                       };
+               };
+       };
+
+       osc: osc {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       clk_rtc: clk_rtc {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac0_rmii_refin: gmac0_rmii_refin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac1_rmii_refin: gmac1_rmii_refin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2stx_bclk_ext: i2stx_bclk_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2stx_lrck_ext: i2stx_lrck_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2srx_bclk_ext: i2srx_bclk_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2srx_lrck_ext: i2srx_lrck_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       tdm_ext: tdm_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       mclk_ext: mclk_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&plic>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               clint: clint@2000000 {
+                       compatible = "starfive,jh7110-clint", "sifive,clint0";
+                       reg = <0x0 0x2000000 0x0 0x10000>;
+                       interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+                                             <&cpu1_intc 3>, <&cpu1_intc 7>,
+                                             <&cpu2_intc 3>, <&cpu2_intc 7>,
+                                             <&cpu3_intc 3>, <&cpu3_intc 7>,
+                                             <&cpu4_intc 3>, <&cpu4_intc 7>;
+               };
+
+               plic: plic@c000000 {
+                       compatible = "starfive,jh7110-plic", 
"sifive,plic-1.0.0";
+                       reg = <0x0 0xc000000 0x0 0x4000000>;
+                       interrupts-extended = <&cpu0_intc 11>,
+                                             <&cpu1_intc 11>, <&cpu1_intc 9>,
+                                             <&cpu2_intc 11>, <&cpu2_intc 9>,
+                                             <&cpu3_intc 11>, <&cpu3_intc 9>,
+                                             <&cpu4_intc 11>, <&cpu4_intc 9>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       #address-cells = <0>;
+                       riscv,ndev = <136>;
+               };
+
+               ccache: cache-controller@2010000 {
+                       compatible = "starfive,jh7110-ccache", "cache";
+                       reg = <0x0 0x2010000 0x0 0x4000>;
+                       interrupts = <1>, <3>, <4>, <2>;
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-sets = <2048>;
+                       cache-size = <2097152>;
+                       cache-unified;
+               };
+
+               syscrg: clock-controller@13020000 {
+                       compatible = "starfive,jh7110-syscrg";
+                       reg = <0x0 0x13020000 0x0 0x10000>;
+                       clocks = <&osc>, <&gmac1_rmii_refin>,
+                                <&gmac1_rgmii_rxin>,
+                                <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+                                <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+                                <&tdm_ext>, <&mclk_ext>;
+                       clock-names = "osc", "gmac1_rmii_refin",
+                                     "gmac1_rgmii_rxin",
+                                     "i2stx_bclk_ext", "i2stx_lrck_ext",
+                                     "i2srx_bclk_ext", "i2srx_lrck_ext",
+                                     "tdm_ext", "mclk_ext";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               aoncrg: clock-controller@17000000 {
+                       compatible = "starfive,jh7110-aoncrg";
+                       reg = <0x0 0x17000000 0x0 0x10000>;
+                       clocks = <&osc>, <&clk_rtc>,
+                                <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+                                <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+                                <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>,
+                                <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+                       clock-names = "osc", "clk_rtc", "gmac0_rmii_refin",
+                                     "gmac0_rgmii_rxin", "stg_axiahb",
+                                     "apb_bus_func", "gmac0_gtxclk";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               stgcrg: clock-controller@10230000 {
+                       compatible = "starfive,jh7110-stgcrg";
+                       reg = <0x0 0x10230000 0x0 0x10000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               gpio: gpio@13040000 {
+                       compatible = "starfive,jh7110-sys-pinctrl";
+                       reg = <0x0 0x13040000 0x0 0x10000>;
+                       reg-names = "control";
+                       clocks = <&syscrg JH7110_SYSCLK_IOMUX>;
+                       resets = <&syscrg JH7110_SYSRST_IOMUX>;
+                       interrupts = <86>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpioa: gpio@17020000 {
+                       compatible = "starfive,jh7110-aon-pinctrl";
+                       reg = <0x0 0x17020000 0x0 0x10000>;
+                       reg-names = "control";
+                       resets = <&aoncrg JH7110_AONRST_AON_IOMUX>;
+                       interrupts = <85>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               uart0: serial@10000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10000000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART0_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART0_APB>,
+                                <&syscrg JH7110_SYSRST_UART0_CORE>;
+                       interrupts = <32>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart1: serial@10010000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART1_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART1_APB>,
+                                <&syscrg JH7110_SYSRST_UART1_CORE>;
+                       interrupts = <33>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart2: serial@10020000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART2_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART2_APB>,
+                                <&syscrg JH7110_SYSRST_UART2_CORE>;
+                       interrupts = <34>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart3: serial@12000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12000000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART3_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART3_APB>,
+                                <&syscrg JH7110_SYSRST_UART3_CORE>;
+                       interrupts = <45>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart4: serial@12010000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART4_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART4_APB>,
+                                <&syscrg JH7110_SYSRST_UART4_CORE>;
+                       interrupts = <46>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart5: serial@12020000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART5_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART5_APB>,
+                                <&syscrg JH7110_SYSRST_UART5_CORE>;
+                       interrupts = <47>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               sdio0: mmc@16010000 {
+                       compatible = "snps,dw-mshc";
+                       reg = <0x0 0x16010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
+                                <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+                       clock-names = "biu", "ciu";
+                       resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
+                       reset-names = "reset";
+                       interrupts = <74>;
+                       data-addr = <0>;
+                       fifo-depth = <32>;
+                       fifo-watermark-aligned;
+                       status = "disabled";
+               };
+
+               sdio1: mmc@16020000 {
+                       compatible = "snps,dw-mshc";
+                       reg = <0x0 0x16020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
+                                <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+                       clock-names = "biu", "ciu";
+                       resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
+                       reset-names = "reset";
+                       interrupts = <75>;
+                       data-addr = <0>;
+                       fifo-depth = <32>;
+                       fifo-watermark-aligned;
+                       status = "disabled";
+               };
+
+               qspi: spi@13010000 {
+                       compatible = "cdns,qspi-nor";
+                       reg = <0x0 0x13010000 0x0 0x10000
+                               0x0 0x21000000 0x0 0x400000>;
+                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
+                       clock-names = "clk_ref";
+                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
+                                <&syscrg JH7110_SYSRST_QSPI_REF>;
+                       resets-names = "rst_apb", "rst_ahb", "rst_ref";
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+};
--
2.17.1


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