Add glue code for TI AM62 to the dwc3 driver; Most code adopted from
TI vendor u-boot code.
Signed-off-by: Sjoerd Simons <sjo...@collabora.com>
---
drivers/usb/dwc3/dwc3-generic.c | 102 ++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 78966718d01..cab7b2e928d 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -11,6 +11,7 @@
#include <cpu_func.h>
#include <log.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
@@ -23,7 +24,9 @@
#include <usb.h>
#include "core.h"
#include "gadget.h"
+#include <regmap.h>
#include <reset.h>
+#include <syscon.h>
#include <clk.h>
#include <usb/xhci.h>
#include <asm/gpio.h>
@@ -398,6 +401,104 @@ struct dwc3_glue_ops ti_ops = {
.glue_configure = dwc3_ti_glue_configure,
};
+void dwc3_ti_am62_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+#define USBSS_MODE_CONTROL 0x1c
+#define USBSS_PHY_CONFIG 0x8
+#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1)
+#define USBSS_PHY_VBUS_SEL_SHIFT 1
+#define USBSS_MODE_VALID BIT(0)
+#define PHY_PLL_REFCLK_MASK GENMASK(3, 0)
+static const int dwc3_ti_am62_rate_table[] = { /* in KHZ */
+ 9600,
+ 10000,
+ 12000,
+ 19200,
+ 20000,
+ 24000,
+ 25000,
+ 26000,
+ 38400,
+ 40000,
+ 58000,
+ 50000,
+ 52000,
+};
+
+ struct clk usb2_refclk;
+ int rate_code, i, ret;
+ unsigned long rate;
+ u32 reg;
+ void *usbss;
+ bool vbus_divider;
+ struct regmap *syscon;
+ struct ofnode_phandle_args args;
+
+ usbss = dev_remap_addr_index(dev, 0);
+ if (IS_ERR(usbss)) {
+ dev_err(dev, "can't map IOMEM resource\n");
+ return;
+ }
+
+ ret = clk_get_by_name(dev, "ref", &usb2_refclk);
+ if (ret) {
+ dev_err(dev, "can't get usb2_refclk\n");
+ return;
+ }
+
+ /* Calcuate the rate code */
+ rate = clk_get_rate(&usb2_refclk);
+ rate /= 1000; /* To KHz */
+ for (i = 0; i < ARRAY_SIZE(dwc3_ti_am62_rate_table); i++) {
+ if (dwc3_ti_am62_rate_table[i] == rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(dwc3_ti_am62_rate_table)) {
+ dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate);
+ return;
+ }
+
+ rate_code = i;
+
+ /* Read the syscon property */
+ syscon = syscon_regmap_lookup_by_phandle(dev,
"ti,syscon-phy-pll-refclk");
+ if (IS_ERR(syscon)) {
+ dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n");
+ return;
+ }
+
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev),
"ti,syscon-phy-pll-refclk", NULL, 1,
+ 0, &args);
+ if (ret)
+ return;
+
+ /* Program PHY PLL refclk by reading syscon property */
+ ret = regmap_update_bits(syscon, args.args[0], PHY_PLL_REFCLK_MASK,
rate_code);
+ if (ret) {
+ dev_err(dev, "failed to set phy pll reference clock rate\n");
+ return;
+ }
+
+ /* VBUS divider select */
+ reg = readl(usbss + USBSS_PHY_CONFIG);
+ vbus_divider = dev_read_bool(dev, "ti,vbus-divider");
+ if (vbus_divider)
+ reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT;
+
+ writel(reg, usbss + USBSS_PHY_CONFIG);
+
+ /* Set mode valid */
+ reg = readl(usbss + USBSS_MODE_CONTROL);
+ reg |= USBSS_MODE_VALID;
+ writel(reg, usbss + USBSS_MODE_CONTROL);
+}
+
+struct dwc3_glue_ops ti_am62_ops = {
+ .glue_configure = dwc3_ti_am62_glue_configure,
+};
+
static int dwc3_glue_bind(struct udevice *parent)
{
ofnode node;
@@ -570,6 +671,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "ti,keystone-dwc3"},
{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
+ { .compatible = "ti,am62-usb", .data = (ulong)&ti_am62_ops },
{ .compatible = "ti,am654-dwc3" },
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
--
2.39.0
