[PATCH 27/41] imx: s4mu: Update MU TR registers count

[Peng Fan (OSS)]

From: Ye Li <ye...@nxp.com>

According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg

Reviewed-by: Peng Fan <peng....@nxp.com>
Signed-off-by: Ye Li <ye...@nxp.com>
Signed-off-by: Peng Fan <peng....@nxp.com>
---
 drivers/misc/sentinel/ele_mu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/sentinel/ele_mu.c b/drivers/misc/sentinel/ele_mu.c
index 63373ea614f..f18ac92adef 100644
--- a/drivers/misc/sentinel/ele_mu.c
+++ b/drivers/misc/sentinel/ele_mu.c
@@ -22,7 +22,7 @@ struct imx8ulp_mu {
 
 #define MU_SR_TE0_MASK         BIT(0)
 #define MU_SR_RF0_MASK         BIT(0)
-#define MU_TR_COUNT            4
+#define MU_TR_COUNT            8
 #define MU_RR_COUNT            4
 
 void mu_hal_init(ulong base)
@@ -65,7 +65,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
        u32 val;
        int ret;
 
-       assert(reg_index < MU_TR_COUNT);
+       assert(reg_index < MU_RR_COUNT);
 
        debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));
 
-- 
2.36.0