From: Hai Pham <hai.pham...@renesas.com>
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent. Add a new
macro to describe it, reusing the existing clock type for R-Car E3.
As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.
Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.
Signed-off-by: Hai Pham <hai.pham...@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+rene...@mailbox.org> # Add D3 tweaks
---
drivers/clk/renesas/clk-rcar-gen3.c | 31 +++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 84bd7fe8b00..aea8b1e8390 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -358,6 +358,37 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
CPG_RPCCKCR_DIV_POST_MASK,
cpg_rpcsrc_div_table,
"RPCSRC");
+ case CLK_TYPE_GEN3_D3_RPCSRC:
+ case CLK_TYPE_GEN3_E3_RPCSRC:
+ /*
+ * Register RPCSRC as fixed factor clock based on the
+ * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
+ * which has been set prior to booting the kernel.
+ */
+ value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
+
+ switch (value) {
+ case 0:
+ div = 5;
+ break;
+ case 1:
+ div = 3;
+ break;
+ case 2:
+ div = core->div;
+ break;
+ case 3:
+ default:
+ div = 2;
+ break;
+ }
+
+ rate = gen3_clk_get_rate64(&parent) / div;
+ debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u =>
rate=%llu\n",
+ __func__, __LINE__, (core->parent >> 16) & 0xffff, div,
rate);
+
+ return rate;
+
case CLK_TYPE_GEN3_RPC:
case CLK_TYPE_GEN4_RPC:
return rcar_clk_get_rate64_div_table(core->parent,
--
2.39.0
