Hi,
On 1/18/23 02:07, John Keeping wrote:
> The RK3288 TRM states that, for 8-bit DDR modes:
>
> The CLKDIV register should always be programmed with a value
> higher than zero (0); that is, a clock divider should always be
> used for 8-bit DDR mode.
>
> In Linux, the driver applies this logic for all SoCs using the driver
> and does not distinguish RK3288, so presumably this requirement is the
> same for all other Rockchip SoCs using this IP.
>
> Add the necessary code to double the clock frequency when 8-bit DDR is
> selected. The dw_mmc core already handles setting CLKDIV correctly
> given the input clock and desired bus clock.
>
> Signed-off-by: John Keeping <j...@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.ch...@samsung.com>
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/rockchip_dw_mmc.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> index 573bf16c87..3661ce3314 100644
> --- a/drivers/mmc/rockchip_dw_mmc.c
> +++ b/drivers/mmc/rockchip_dw_mmc.c
> @@ -41,6 +41,14 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host
> *host, uint freq)
> struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
> int ret;
>
> + /*
> + * The clock frequency chosen here affects CLKDIV in the dw_mmc core.
> + * That can be either 0 or 1, but it must be set to 1 for eMMC DDR52
> + * 8-bit mode. It will be set to 0 for all other modes.
> + */
> + if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
> + freq *= 2;
> +
> ret = clk_set_rate(&priv->clk, freq);
> if (ret < 0) {
> debug("%s: err=%d\n", __func__, ret);
