> From: Peter Yu-Chien Lin(林宇謙) <peter...@andestech.com> > Sent: Monday, February 06, 2023 4:11 PM > To: u-boot@lists.denx.de > Cc: Leo Yu-Chi Liang(梁育齊) <ycli...@andestech.com>; Rick Jian-Zhi Chen(陳建志) > <r...@andestech.com>; prabhakar.cse...@gmail.com; Peter Yu-Chien Lin(林宇謙) > <peter...@andestech.com> > Subject: [PATCH v2 04/10] riscv: cpu: ax25: Simplify cache enabling logic in > harts_early_init() > > As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in > harts_early_init() and do not disable in cleanup_before_linux(). This patch > also simplifies the logic and moves the CSR encoding to > include/asm/arch-andes/csr.h. > > [0] > https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa > > Signed-off-by: Yu Chien Peter Lin <peter...@andestech.com> > Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com> > --- > arch/riscv/cpu/ax25/cpu.c | 49 ++++++------------------- > arch/riscv/include/asm/arch-andes/csr.h | 29 +++++++++++++++ > 2 files changed, 41 insertions(+), 37 deletions(-) create mode 100644 > arch/riscv/include/asm/arch-andes/csr.h
Reviewed-by: Rick Chen <r...@andestech.com>
