On Sun, Feb 12, 2023 at 12:25:56PM -0700, Simon Glass wrote: > On Sun, 12 Feb 2023 at 00:01, Yu Chien Peter Lin <peter...@andestech.com> > wrote: > > > > This patch adds a brief introduction to the RISC-V architecture and > > the typical boot process used on a variety of RISC-V platforms. > > > > Signed-off-by: Yu Chien Peter Lin <peter...@andestech.com> > > --- > > Hi RISC-V community, > > > > Please leave a comment if there is anything I've missed that should > > be mentioned in the document. Thanks. > > --- > > doc/arch/index.rst | 1 + > > doc/arch/riscv.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 44 insertions(+) > > create mode 100644 doc/arch/riscv.rst > > Reviewed-by: Simon Glass <s...@chromium.org> > > Looks good. One nit is that we try to talk in terms of boot 'phases' > rather than stages.
Hi Simon, Thanks for the review, I'll update in the next patch. Best regards, Peter Lin > Regards, > Simon
