On Tue, 21 Feb 2023 at 13:01, Dylan Hung <dylan_h...@aspeedtech.com> wrote: > > According to the PLL vendor, we should keep the PLL power on, so we > shouldn't toggle the power-down bit during PLL initialization. > > Signed-off-by: Dylan Hung <dylan_h...@aspeedtech.com>
Reviewed-by: Joel Stanley <j...@jms.id.au> > --- > drivers/clk/aspeed/clk_ast2600.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/clk/aspeed/clk_ast2600.c > b/drivers/clk/aspeed/clk_ast2600.c > index 0df1dc3718d3..e5ada5b6d49c 100644 > --- a/drivers/clk/aspeed/clk_ast2600.c > +++ b/drivers/clk/aspeed/clk_ast2600.c > @@ -538,7 +538,7 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu > *scu, > } > > p_cfg->reg.b.bypass = 0; > - p_cfg->reg.b.off = 1; > + p_cfg->reg.b.off = 0; > p_cfg->reg.b.reset = 1; > > reg = readl(addr); > @@ -549,7 +549,6 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu > *scu, > /* write extend parameter */ > writel(p_cfg->ext_reg, addr_ext); > udelay(100); > - p_cfg->reg.b.off = 0; > p_cfg->reg.b.reset = 0; > reg &= ~GENMASK(25, 0); > reg |= p_cfg->reg.w; > -- > 2.25.1 >