On Sat, Feb 25, 2023 at 9:38 AM Dario Binacchi
<dario.binac...@amarulasolutions.com> wrote:
>
> During some tests to check the pixel clock rate in the transition from
> U-Boot to the Linux kernel, I noticed that with the same configuration
> of the registers the debug messages reported different rates.
>
> The same Linux kernel calculations are now used to get the PLL video
> rate.
>
> Signed-off-by: Dario Binacchi <dario.binac...@amarulasolutions.com>
> ---
>
> arch/arm/mach-imx/mx6/clock.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
> index cb9d629be408..17d8dcd5c841 100644
> --- a/arch/arm/mach-imx/mx6/clock.c
> +++ b/arch/arm/mach-imx/mx6/clock.c
> @@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
> static u32 decode_pll(enum pll_clocks pll, u32 infreq)
> {
> u32 div, test_div, pll_num, pll_denom;
> + u64 temp64;
>
> switch (pll) {
> case PLL_SYS:
> @@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
> }
> test_div = 1 << (2 - test_div);
>
> - return infreq * (div + pll_num / pll_denom) / test_div;
> + temp64 = (u64)infreq;
> + temp64 *= pll_num;
> + do_div(temp64, pll_denom);
> + return infreq * div + (unsigned long)temp64;
> default:
> return 0;
Reviewed-by: Michael Trimarchi <mich...@amarulasolutions.com>
> }
> --
> 2.32.0
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
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T. +31 (0)85 111 9172
i...@amarulasolutions.com
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