Hello! I'm not rockchip maintainer, how many times I need to repeat it to not send me rockchip patches? Or is there something important for me?
On Tuesday 11 April 2023 18:14:49 Tianling Shen wrote: > The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC > chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. > > The device tree is taken from the kernel linux-next branch: > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9 > > Signed-off-by: Tianling Shen <cns...@gmail.com> > --- > Changes in v2: > Added missing defconfig. > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi | 3 + > arch/arm/dts/rk3328-nanopi-r2c.dts | 40 ++++++++ > board/rockchip/evb_rk3328/MAINTAINERS | 6 ++ > configs/nanopi-r2c-rk3328_defconfig | 112 +++++++++++++++++++++ > 5 files changed, 162 insertions(+) > create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi > create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts > create mode 100644 configs/nanopi-r2c-rk3328_defconfig > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 337bee7e1e..816e068f33 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -123,6 +123,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ > > dtb-$(CONFIG_ROCKCHIP_RK3328) += \ > rk3328-evb.dtb \ > + rk3328-nanopi-r2c.dtb \ > rk3328-nanopi-r2s.dtb \ > rk3328-roc-cc.dtb \ > rk3328-rock64.dtb \ > diff --git a/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi > b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi > new file mode 100644 > index 0000000000..2ab32cf00a > --- /dev/null > +++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi > @@ -0,0 +1,3 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > + > +#include "rk3328-nanopi-r2s-u-boot.dtsi" > diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts > b/arch/arm/dts/rk3328-nanopi-r2c.dts > new file mode 100644 > index 0000000000..a07a26b944 > --- /dev/null > +++ b/arch/arm/dts/rk3328-nanopi-r2c.dts > @@ -0,0 +1,40 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. > + * (http://www.friendlyarm.com) > + * > + * Copyright (c) 2021-2023 Tianling Shen <cns...@gmail.com> > + */ > + > +/dts-v1/; > +#include "rk3328-nanopi-r2s.dts" > + > +/ { > + model = "FriendlyElec NanoPi R2C"; > + compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; > +}; > + > +&gmac2io { > + phy-handle = <&yt8521s>; > + tx_delay = <0x22>; > + rx_delay = <0x12>; > + > + mdio { > + /delete-node/ ethernet-phy@1; > + > + yt8521s: ethernet-phy@3 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <3>; > + > + motorcomm,clk-out-frequency-hz = <125000000>; > + motorcomm,keep-pll-enabled; > + motorcomm,auto-sleep-disabled; > + > + pinctrl-0 = <ð_phy_reset_pin>; > + pinctrl-names = "default"; > + reset-assert-us = <10000>; > + reset-deassert-us = <50000>; > + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; > + }; > + }; > +}; > diff --git a/board/rockchip/evb_rk3328/MAINTAINERS > b/board/rockchip/evb_rk3328/MAINTAINERS > index 14fda46e8f..3c46613ab5 100644 > --- a/board/rockchip/evb_rk3328/MAINTAINERS > +++ b/board/rockchip/evb_rk3328/MAINTAINERS > @@ -5,6 +5,12 @@ F: board/rockchip/evb_rk3328 > F: include/configs/evb_rk3328.h > F: configs/evb-rk3328_defconfig > > +NANOPI-R2C-RK3328 > +M: Tianling Shen <cns...@gmail.com> > +S: Maintained > +F: configs/nanopi-r2c-rk3328_defconfig > +F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi > + > NANOPI-R2S-RK3328 > M: David Bauer <m...@david-bauer.net> > S: Maintained > diff --git a/configs/nanopi-r2c-rk3328_defconfig > b/configs/nanopi-r2c-rk3328_defconfig > new file mode 100644 > index 0000000000..1460ab32f5 > --- /dev/null > +++ b/configs/nanopi-r2c-rk3328_defconfig > @@ -0,0 +1,112 @@ > +CONFIG_ARM=y > +CONFIG_SKIP_LOWLEVEL_INIT=y > +CONFIG_COUNTER_FREQUENCY=24000000 > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_TEXT_BASE=0x00200000 > +CONFIG_SPL_GPIO=y > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 > +CONFIG_ENV_OFFSET=0x3F8000 > +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" > +CONFIG_DM_RESET=y > +CONFIG_ROCKCHIP_RK3328=y > +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y > +CONFIG_TPL_LIBCOMMON_SUPPORT=y > +CONFIG_TPL_LIBGENERIC_SUPPORT=y > +CONFIG_SPL_DRIVERS_MISC=y > +CONFIG_SPL_STACK_R_ADDR=0x600000 > +CONFIG_SPL_STACK=0x400000 > +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 > +CONFIG_DEBUG_UART_BASE=0xFF130000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SYS_LOAD_ADDR=0x800800 > +CONFIG_DEBUG_UART=y > +# CONFIG_ANDROID_BOOT_IMAGE is not set > +CONFIG_FIT=y > +CONFIG_FIT_VERBOSE=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_MISC_INIT_R=y > +CONFIG_SPL_MAX_SIZE=0x40000 > +CONFIG_SPL_PAD_TO=0x7f8000 > +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > +CONFIG_SPL_BSS_START_ADDR=0x2000000 > +CONFIG_SPL_BSS_MAX_SIZE=0x2000 > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set > +CONFIG_SPL_STACK_R=y > +CONFIG_SPL_I2C=y > +CONFIG_SPL_POWER=y > +CONFIG_SPL_ATF=y > +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > +CONFIG_TPL_SYS_MALLOC_SIMPLE=y > +CONFIG_CMD_BOOTZ=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_TIME=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_TPL_OF_CONTROL=y > +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks > assigned-clock-rates assigned-clock-parents" > +CONFIG_TPL_OF_PLATDATA=y > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_SYS_MMC_ENV_DEV=1 > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_TPL_DM=y > +CONFIG_REGMAP=y > +CONFIG_SPL_REGMAP=y > +CONFIG_TPL_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_SPL_SYSCON=y > +CONFIG_TPL_SYSCON=y > +CONFIG_CLK=y > +CONFIG_SPL_CLK=y > +CONFIG_FASTBOOT_BUF_ADDR=0x800800 > +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SF_DEFAULT_SPEED=20000000 > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_SPL_PMIC_RK8XX=y > +CONFIG_SPL_DM_REGULATOR=y > +CONFIG_REGULATOR_PWM=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_SPL_DM_REGULATOR_FIXED=y > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_RAM=y > +CONFIG_SPL_RAM=y > +CONFIG_TPL_RAM=y > +CONFIG_BAUDRATE=1500000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550_MEM32=y > +CONFIG_SYSINFO=y > +CONFIG_SYSRESET=y > +# CONFIG_TPL_SYSRESET is not set > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > +CONFIG_USB_DWC2=y > +CONFIG_USB_DWC3=y > +# CONFIG_USB_DWC3_GADGET is not set > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_DWC2_OTG=y > +CONFIG_SPL_TINY_MEMSET=y > +CONFIG_TPL_TINY_MEMSET=y > +CONFIG_ERRNO_STR=y > -- > 2.40.0 >