[PATCH v2 9/9] arm: dts: sdm845: add GENI SE QUP device tree node

[Vladimir Zapolskiy]

On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.

The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapols...@linaro.org>
---
 arch/arm/dts/dragonboard845c.dts |  2 +-
 arch/arm/dts/sdm845.dtsi         | 25 +++++++++++++++----------
 arch/arm/dts/starqltechn.dts     |  2 +-
 3 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
index 1722dce33ff2..b4f057ac6537 100644
--- a/arch/arm/dts/dragonboard845c.dts
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -21,7 +21,7 @@
        };
 
        aliases {
-               serial0 = &debug_uart;
+               serial0 = &uart9;
        };
 
        memory {
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 92bdc82177d6..3b86b9328fc6 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -51,16 +51,21 @@
                        };
                };
 
-               debug_uart: serial@a84000 {
-                       compatible = "qcom,geni-debug-uart";
-                       reg = <0xa84000 0x4000>;
-                       reg-names = "se_phys";
-                       clock-names = "se";
-                       clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&qup_uart9>;
-                       qcom,wrapper-core = <0x8a>;
-                       status = "disabled";
+               qupv3_id_1: geniqup@ac0000 {
+                       compatible = "qcom,geni-se-qup";
+                       reg = <0x00ac0000 0x6000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       uart9: serial@a84000 {
+                               compatible = "qcom,geni-debug-uart";
+                               reg = <0xa84000 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_uart9>;
+                       };
                };
 
                spmi@c440000 {
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index 34a4f59cbd17..dcbc3b6d4966 100644
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -21,7 +21,7 @@
        };
 
        aliases {
-               serial0 = &debug_uart;
+               serial0 = &uart9;
        };
 
        memory {
-- 
2.33.0