[PATCH 2/7] pci: pcie_dw_rockchip: Support max_link_speed dts property

[Eugen Hristev]

From: Jon Lin <jon....@rock-chips.com>

Add support for max_link_speed specified in the PCI DT binding.

Signed-off-by: Jon Lin <jon....@rock-chips.com>
[eugen.hris...@collabora.com: port to latest API, set default correctly,
align to 80 chars]
Signed-off-by: Eugen Hristev <eugen.hris...@collabora.com>
---
 drivers/pci/pcie_dw_rockchip.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index ff121046604a..6a2a5e15646e 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -42,6 +42,7 @@ struct rk_pcie {
        struct clk_bulk clks;
        struct reset_ctl_bulk   rsts;
        struct gpio_desc        rst_gpio;
+       u32             gen;
 };
 
 /* Parameters for the waiting for iATU enabled routine */
@@ -331,7 +332,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
        rk_pcie_writel_apb(priv, 0x0, 0xf00040);
        pcie_dw_setup_host(&priv->dw);
 
-       ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
+       ret = rk_pcie_link_up(priv, priv->gen);
        if (ret < 0)
                goto err_link_up;
 
@@ -351,6 +352,7 @@ err_exit_phy:
 static int rockchip_pcie_parse_dt(struct udevice *dev)
 {
        struct rk_pcie *priv = dev_get_priv(dev);
+       u32 max_link_speed;
        int ret;
 
        priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
@@ -397,6 +399,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
                goto rockchip_pcie_parse_dt_err_phy_get_by_index;
        }
 
+       ret = ofnode_read_u32(dev_ofnode(dev), "max-link-speed",
+                             &max_link_speed);
+       if (ret < 0 || max_link_speed > 4)
+               priv->gen = LINK_SPEED_GEN_3;
+       else
+               priv->gen = max_link_speed;
+
        return 0;
 
 rockchip_pcie_parse_dt_err_phy_get_by_index:
-- 
2.34.1