On 3/8/23 21:26, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siem...@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas RCAR2/3
R-Car , not RCAR .
[...]
+static int r9a06g032_clk_probe(struct udevice *dev)
+{
+ struct r9a06g032_priv *priv = dev_get_priv(dev);
+ int err;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_dbg(dev, "unable to find regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ /* Enable S/W reset */
+ regmap_write(priv->regmap, 0x120, 0x41);
+
+ /* Get master clock */
+ err = clk_get_by_name(dev, "mclk", &priv->mclk);
+ if (err)
+ return err;
+
+ return 0;
You can use 'return clk_get_by_name(...)' here directly instead of the
'
err = ...
if (err)
return err;
return 0;
'
