Sync the devicetree files from the sunxi Linux queue [1], to match
the Linux 6.4-rc pull request. Those patches are in Linux-next for a bit
now. This is covering both 64-bit and 32-bit Allwinner SoCs with Arm
Ltd. cores, we skip the new RISC-V bits for now, as sunxi RISC-V support
for U-Boot is still work in progress.

Among smaller cosmetic changes, this adds a SATA regulator node which we
need in U-Boot to get rid of hard-coded GPIOs.
Also this updates the Allwinner F1C100s DTs, adding its USB nodes, and
also adding the DTs for two new boards.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/commit/?h=sunxi/dt-for-6.4&id=20c5db6c3d79d357c9d787edad3bbf03d98a08bf

Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
 arch/arm/dts/sun50i-h5-orangepi-pc2.dts      |  1 +
 arch/arm/dts/sun5i-gr8-chip-pro.dts          |  2 +-
 arch/arm/dts/sun5i-r8-chip.dts               |  2 +-
 arch/arm/dts/sun6i-a31s-sina31s.dts          |  2 +-
 arch/arm/dts/sun8i-a33.dtsi                  |  1 +
 arch/arm/dts/sun8i-a83t-bananapi-m3.dts      | 15 ++++
 arch/arm/dts/sun8i-h3-beelink-x2.dts         |  2 +-
 arch/arm/dts/sun8i-h3-nanopi-duo2.dts        |  2 +-
 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++
 arch/arm/dts/suniv-f1c100s.dtsi              | 32 ++++++++
 arch/arm/dts/suniv-f1c200s-lctech-pi.dts     | 76 ++++++++++++++++++
 arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts | 81 ++++++++++++++++++++
 12 files changed, 227 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/dts/suniv-f1c200s-lctech-pi.dts
 create mode 100644 arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts

diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts 
b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
index b5c1ff19b4c..ce3ae19e72d 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -3,6 +3,7 @@
 
 /dts-v1/;
 #include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
diff --git a/arch/arm/dts/sun5i-gr8-chip-pro.dts 
b/arch/arm/dts/sun5i-gr8-chip-pro.dts
index a32cde3e32e..5c3562b85a5 100644
--- a/arch/arm/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/dts/sun5i-gr8-chip-pro.dts
@@ -70,7 +70,7 @@
        leds {
                compatible = "gpio-leds";
 
-               status {
+               led-0 {
                        label = "chip-pro:white:status";
                        gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
                        default-state = "on";
diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts
index 4bf4943d4eb..fd37bd1f392 100644
--- a/arch/arm/dts/sun5i-r8-chip.dts
+++ b/arch/arm/dts/sun5i-r8-chip.dts
@@ -70,7 +70,7 @@
        leds {
                compatible = "gpio-leds";
 
-               status {
+               led-0 {
                        label = "chip:white:status";
                        gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
                        default-state = "on";
diff --git a/arch/arm/dts/sun6i-a31s-sina31s.dts 
b/arch/arm/dts/sun6i-a31s-sina31s.dts
index 0af48e143b6..56956352914 100644
--- a/arch/arm/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/dts/sun6i-a31s-sina31s.dts
@@ -67,7 +67,7 @@
        leds {
                compatible = "gpio-leds";
 
-               status {
+               led-0 {
                        label = "sina31s:status:usr";
                        gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
                };
diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi
index b3d1bdfb511..30fdd2703b1 100644
--- a/arch/arm/dts/sun8i-a33.dtsi
+++ b/arch/arm/dts/sun8i-a33.dtsi
@@ -278,6 +278,7 @@
                dphy: d-phy@1ca1000 {
                        compatible = "allwinner,sun6i-a31-mipi-dphy";
                        reg = <0x01ca1000 0x1000>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_BUS_MIPI_DSI>,
                                 <&ccu CLK_DSI_DPHY>;
                        clock-names = "bus", "mod";
diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts 
b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
index b60016a4429..197cf6959b5 100644
--- a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
@@ -105,6 +105,21 @@
                /* enables internal regulator and de-asserts reset */
                reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
        };
+
+       /*
+        * Power supply for the SATA disk, behind a USB-SATA bridge.
+        * Since it is a USB device, there is no consumer in the DT, so we
+        * have to keep this always on.
+        */
+       regulator-sata-disk-pwr {
+               compatible = "regulator-fixed";
+               regulator-name = "sata-disk-pwr";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+               enable-active-high;
+               gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
+       };
 };
 
 &cpu0 {
diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts 
b/arch/arm/dts/sun8i-h3-beelink-x2.dts
index 27a0d51289d..a6d38ecee14 100644
--- a/arch/arm/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts
@@ -57,7 +57,7 @@
                ethernet1 = &sdiowifi;
        };
 
-       cec-gpio {
+       cec {
                compatible = "cec-gpio";
                cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* 
PA14 */
                hdmi-phandle = <&hdmi>;
diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts 
b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts
index 43641cb8239..343b02b9715 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts
@@ -57,7 +57,7 @@
                regulator-ramp-delay = <50>; /* 4ms */
 
                enable-active-high;
-               enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+               enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
                gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
                gpios-states = <0x1>;
                states = <1100000 0>, <1300000 1>;
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts 
b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
index 04e59b8381c..43896723a99 100644
--- a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 #include "suniv-f1c100s.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
        model = "Lichee Pi Nano";
        compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -50,8 +52,22 @@
        };
 };
 
+&otg_sram {
+       status = "okay";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_pe_pins>;
        status = "okay";
 };
+
+&usb_otg {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&usbphy {
+       usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+       status = "okay";
+};
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
index 9455d27e516..3c61d59ab5f 100644
--- a/arch/arm/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -133,6 +133,32 @@
                        #size-cells = <0>;
                };
 
+               usb_otg: usb@1c13000 {
+                       compatible = "allwinner,suniv-f1c100s-musb";
+                       reg = <0x01c13000 0x0400>;
+                       clocks = <&ccu CLK_BUS_OTG>;
+                       resets = <&ccu RST_BUS_OTG>;
+                       interrupts = <26>;
+                       interrupt-names = "mc";
+                       phys = <&usbphy 0>;
+                       phy-names = "usb";
+                       extcon = <&usbphy 0>;
+                       allwinner,sram = <&otg_sram 1>;
+                       status = "disabled";
+               };
+
+               usbphy: phy@1c13400 {
+                       compatible = "allwinner,suniv-f1c100s-usb-phy";
+                       reg = <0x01c13400 0x10>;
+                       reg-names = "phy_ctrl";
+                       clocks = <&ccu CLK_USB_PHY0>;
+                       clock-names = "usb0_phy";
+                       resets = <&ccu RST_USB_PHY0>;
+                       reset-names = "usb0_reset";
+                       #phy-cells = <1>;
+                       status = "disabled";
+               };
+
                ccu: clock@1c20000 {
                        compatible = "allwinner,suniv-f1c100s-ccu";
                        reg = <0x01c20000 0x400>;
@@ -181,6 +207,12 @@
                                pins = "PE0", "PE1";
                                function = "uart0";
                        };
+
+                       /omit-if-no-ref/
+                       uart1_pa_pins: uart1-pa-pins {
+                               pins = "PA2", "PA3";
+                               function = "uart1";
+                       };
                };
 
                i2c0: i2c@1c27000 {
diff --git a/arch/arm/dts/suniv-f1c200s-lctech-pi.dts 
b/arch/arm/dts/suniv-f1c200s-lctech-pi.dts
new file mode 100644
index 00000000000..2d2a3f026df
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c200s-lctech-pi.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Arm Ltd,
+ * based on work:
+ *   Copyright 2022 Icenowy Zheng <u...@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "Lctech Pi F1C200s";
+       compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
+                    "allwinner,suniv-f1c100s";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       reg_vcc3v3: regulator-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+};
+
+&mmc0 {
+       broken-cd;
+       bus-width = <4>;
+       disable-wp;
+       vmmc-supply = <&reg_vcc3v3>;
+       status = "okay";
+};
+
+&otg_sram {
+       status = "okay";
+};
+
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi0_pc_pins>;
+       status = "okay";
+
+       flash@0 {
+               compatible = "spi-nand";
+               reg = <0>;
+               spi-max-frequency = <40000000>;
+       };
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_pa_pins>;
+       status = "okay";
+};
+
+/*
+ * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected
+ * to Vin, which supplies the board. Host mode works (if the board is powered
+ * otherwise), but peripheral is probably the intention.
+ */
+&usb_otg {
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
+&usbphy {
+       status = "okay";
+};
diff --git a/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts 
b/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
new file mode 100644
index 00000000000..184c245041a
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Icenowy Zheng <u...@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       model = "Popcorn Computer PopStick v1.1";
+       compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
+                    "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led {
+                       function = LED_FUNCTION_STATUS;
+                       color = <LED_COLOR_ID_GREEN>;
+                       gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       reg_vcc3v3: regulator-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+};
+
+&mmc0 {
+       cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
+       bus-width = <4>;
+       disable-wp;
+       vmmc-supply = <&reg_vcc3v3>;
+       status = "okay";
+};
+
+&otg_sram {
+       status = "okay";
+};
+
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi0_pc_pins>;
+       status = "okay";
+
+       flash@0 {
+               compatible = "spi-nand";
+               reg = <0>;
+               spi-max-frequency = <40000000>;
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pe_pins>;
+       status = "okay";
+};
+
+&usb_otg {
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
+&usbphy {
+       status = "okay";
+};
-- 
2.35.7

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