Hi Zixun Li,

On 4/27/23 22:51, Zixun Li wrote:
Hardware: SAMA5D27 customized board, EMMC connected to SDMMC0. SDMMC0_CD pin 
pulled-down for BootROM card detection, once booted it used as LED output.

Software: u-boot-at91 76f7f55

Issue:
U-Boot can't detect EMMC despite it set to non-removable in DT, unless 
SDMMC0_CD pin is used (so this pin can't be used for other purpose)

sdmmc0: sdio-host@a0000000 {
                                                 bus-width = <4>;
                                                 pinctrl-names = "default";
                                                 pinctrl-0 = 
<&pinctrl_sdmmc0_default>;
                                                 status = "okay";
                                                 non-removable;
                                                 no-1-8-v;
                                 };

Workaround: I have to FCD bit of SDMMC_MC1R register.

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 766e4a6b0c..89ceeaf3c1 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -758,7 +758,12 @@ static int sdhci_get_cd(struct udevice *dev)

         /* If nonremovable, assume that the card is always present. */
         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+       {
+               value = sdhci_readb(host, SDHCI_HOST_MC1R);
+               sdhci_writeb(host, SDHCI_VENDOR_MC1R_FCD | value, 
SDHCI_HOST_MC1R);
                 return 1;
+       }
+

Can you find some place to set this bit in the atmel sdhci driver, and not in the core?
The MC1R register is specific to at91 device.

Eugen

         /* If polling, assume that the card is always present. */
         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
                 return 1;
diff --git a/include/sdhci.h b/include/sdhci.h
index c718dd7206..61e7ebb2a1 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -223,6 +223,9 @@

#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)

+#define SDHCI_HOST_MC1R                        0x204
+
+#define SDHCI_VENDOR_MC1R_FCD  0x80
/*
   * End of controller registers.
   */


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