On 2023/4/23 02:19, Jonas Karlman wrote:
Update config, IO and memory regions used based on [1] with pcie3x2
config reg size corrected from 16 to 1 MiB.
[1] https://lore.kernel.org/lkml/20221112114125.1637543-2-ahol...@omnom.net/
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
---
arch/arm/dts/rk3568.dtsi | 14 ++++++++------
arch/arm/dts/rk356x.dtsi | 7 ++++---
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index ba67b58f05b7..f1be76a54ceb 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -94,9 +94,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0400000 0x0 0x00400000>,
<0x0 0xfe270000 0x0 0x00010000>,
- <0x3 0x7f000000 0x0 0x01000000>;
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0
0x00100000>,
- <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0
0x3ef00000>;
+ <0x0 0xf2000000 0x0 0x00100000>;
+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0
0x00100000>,
+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0
0x01e00000>,
+ <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0
0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
@@ -146,9 +147,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0800000 0x0 0x00400000>,
<0x0 0xfe280000 0x0 0x00010000>,
- <0x3 0xbf000000 0x0 0x01000000>;
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0
0x00100000>,
- <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0
0x3ef00000>;
+ <0x0 0xf0000000 0x0 0x00100000>;
+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0
0x00100000>,
+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0
0x01e00000>,
+ <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0
0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 6492ace0de6b..e0591c194bec 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -951,7 +951,7 @@
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc0000000 0x0 0x00400000>,
<0x0 0xfe260000 0x0 0x00010000>,
- <0x3 0x3f000000 0x0 0x01000000>;
+ <0x0 0xf4000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -980,8 +980,9 @@
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0
0x00100000
- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0
0x3ef00000>;
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0
0x00100000>,
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0
0x01e00000>,
+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0
0x40000000>;
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;
