On 15/05/23 4:20 pm, Ravi Gunasekaran wrote:
> Add support for j721s2-wiz-10g device to use clock-names interface
> instead of explicitly defining clock nodes within device tree node.
>
> Signed-off-by: Ravi Gunasekaran <r-gunaseka...@ti.com>
> ---
> drivers/phy/ti/phy-j721e-wiz.c | 21 ++++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> index 23397175d3..34314d0bd1 100644
> --- a/drivers/phy/ti/phy-j721e-wiz.c
> +++ b/drivers/phy/ti/phy-j721e-wiz.c
> @@ -256,6 +256,7 @@ enum wiz_type {
> J721E_WIZ_10G,
> AM64_WIZ_10G,
> J784S4_WIZ_10G,
> + J721S2_WIZ_10G,
> };
>
> struct wiz_data {
> @@ -307,6 +308,15 @@ static struct wiz_data j784s4_wiz_10g = {
> .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
> };
>
> +static struct wiz_data j721s2_10g_data = {
> + .type = J721S2_WIZ_10G,
> + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
> + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
> + .refclk_dig_sel = &refclk_dig_sel_10g,
> + .clk_mux_sel = clk_mux_sel_10g,
> + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
> +};
> +
> #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
> #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
>
> @@ -1037,8 +1047,14 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
> ofnode node;
> int i, rc;
>
> - if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G)
> + switch (type) {
> + case AM64_WIZ_10G:
> + case J784S4_WIZ_10G:
> + case J721S2_WIZ_10G:
> return j721e_wiz_bind_clocks(wiz);
> + default:
> + break;
> + };
>
> div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
> if (!div_clk_drv) {
> @@ -1282,6 +1298,9 @@ static const struct udevice_id j721e_wiz_ids[] = {
> {
> .compatible = "ti,j784s4-wiz-10g", .data =
> (ulong)&j784s4_wiz_10g,
> },
> + {
> + .compatible = "ti,j721s2-wiz-10g", .data =
> (ulong)&j721s2_10g_data,
> + },
> {}
> };
>
This patch is needed inorder to sync up the J721S2 SerDes node in
DTS in u-boot with linux kernel.
>
> base-commit: eaa9efafffaf87e3414db5d21face5e2dad105e4
--
Regards,
Ravi
