Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.

This device is similar to the NanoPi R2S, and has a 16MB
SPI NOR (mx25l12805d). The reset button is changed to
directly reset the power supply, another detail is that
both network ports have independent MAC addresses.

The device tree and description are taken from kernel v6.3-rc1.

Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Signed-off-by: Tianling Shen <cns...@gmail.com>
---

Changes in v2:
* Rebased upon the latest git HEAD
* Collected R-b tag.
* Removed kernel link from commit message.

---
 arch/arm/dts/Makefile                         |   1 +
 .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi   |  46 +++
 arch/arm/dts/rk3328-orangepi-r1-plus.dts      | 373 ++++++++++++++++++
 board/rockchip/evb_rk3328/MAINTAINERS         |   6 +
 configs/orangepi-r1-plus-rk3328_defconfig     | 114 ++++++
 5 files changed, 540 insertions(+)
 create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts
 create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..9d189788aa 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
        rk3328-evb.dtb \
        rk3328-nanopi-r2c.dtb \
        rk3328-nanopi-r2s.dtb \
+       rk3328-orangepi-r1-plus.dtb \
        rk3328-roc-cc.dtb \
        rk3328-rock64.dtb \
        rk3328-rock-pi-e.dtb
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi 
b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
new file mode 100644
index 0000000000..637c70adf1
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 David Bauer
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+       chosen {
+               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+       };
+};
+
+&gpio0 {
+       bootph-pre-ram;
+};
+
+&pinctrl {
+       bootph-pre-ram;
+};
+
+&sdmmc0m1_pin {
+       bootph-pre-ram;
+};
+
+&pcfg_pull_up_4ma {
+       bootph-pre-ram;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+       bootph-pre-ram;
+};
+
+&gmac2io {
+       snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 50000>;
+};
+
+&spi0 {
+       spi_flash: spiflash@0 {
+               bootph-all;
+       };
+};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts 
b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
new file mode 100644
index 0000000000..dc83d74045
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Based on rk3328-nanopi-r2s.dts, which is:
+ *   Copyright (c) 2020 David Bauer <m...@david-bauer.net>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3328.dtsi"
+
+/ {
+       model = "Xunlong Orange Pi R1 Plus";
+       compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+
+       aliases {
+               ethernet1 = &rtl8153;
+               mmc0 = &sdmmc;
+       };
+
+       chosen {
+               stdout-path = "serial2:1500000n8";
+       };
+
+       gmac_clk: gmac-clock {
+               compatible = "fixed-clock";
+               clock-frequency = <125000000>;
+               clock-output-names = "gmac_clkin";
+               #clock-cells = <0>;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+               pinctrl-names = "default";
+
+               led-0 {
+                       function = LED_FUNCTION_LAN;
+                       color = <LED_COLOR_ID_GREEN>;
+                       gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+               };
+
+               led-1 {
+                       function = LED_FUNCTION_STATUS;
+                       color = <LED_COLOR_ID_RED>;
+                       gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               led-2 {
+                       function = LED_FUNCTION_WAN;
+                       color = <LED_COLOR_ID_GREEN>;
+                       gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+               };
+       };
+
+       vcc_sd: sdmmc-regulator {
+               compatible = "regulator-fixed";
+               gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+               pinctrl-0 = <&sdmmc0m1_pin>;
+               pinctrl-names = "default";
+               regulator-name = "vcc_sd";
+               regulator-boot-on;
+               vin-supply = <&vcc_io>;
+       };
+
+       vcc_sys: vcc-sys-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc_sys";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+       };
+
+       vdd_5v_lan: vdd-5v-lan-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+               pinctrl-0 = <&lan_vdd_pin>;
+               pinctrl-names = "default";
+               regulator-name = "vdd_5v_lan";
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vcc_sys>;
+       };
+};
+
+&cpu0 {
+       cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+       cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+       cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+       cpu-supply = <&vdd_arm>;
+};
+
+&display_subsystem {
+       status = "disabled";
+};
+
+&gmac2io {
+       assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+       assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+       clock_in_out = "input";
+       phy-handle = <&rtl8211e>;
+       phy-mode = "rgmii";
+       phy-supply = <&vcc_io>;
+       pinctrl-0 = <&rgmiim1_pins>;
+       pinctrl-names = "default";
+       snps,aal;
+       rx_delay = <0x18>;
+       tx_delay = <0x24>;
+       status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               rtl8211e: ethernet-phy@1 {
+                       reg = <1>;
+                       pinctrl-0 = <&eth_phy_reset_pin>;
+                       pinctrl-names = "default";
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <50000>;
+                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+               };
+       };
+};
+
+&i2c1 {
+       status = "okay";
+
+       rk805: pmic@18 {
+               compatible = "rockchip,rk805";
+               reg = <0x18>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+               #clock-cells = <1>;
+               clock-output-names = "xin32k", "rk805-clkout2";
+               gpio-controller;
+               #gpio-cells = <2>;
+               pinctrl-0 = <&pmic_int_l>;
+               pinctrl-names = "default";
+               rockchip,system-power-controller;
+               wakeup-source;
+
+               vcc1-supply = <&vcc_sys>;
+               vcc2-supply = <&vcc_sys>;
+               vcc3-supply = <&vcc_sys>;
+               vcc4-supply = <&vcc_sys>;
+               vcc5-supply = <&vcc_io>;
+               vcc6-supply = <&vcc_sys>;
+
+               regulators {
+                       vdd_log: DCDC_REG1 {
+                               regulator-name = "vdd_log";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <712500>;
+                               regulator-max-microvolt = <1450000>;
+                               regulator-ramp-delay = <12500>;
+
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1000000>;
+                               };
+                       };
+
+                       vdd_arm: DCDC_REG2 {
+                               regulator-name = "vdd_arm";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <712500>;
+                               regulator-max-microvolt = <1450000>;
+                               regulator-ramp-delay = <12500>;
+
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <950000>;
+                               };
+                       };
+
+                       vcc_ddr: DCDC_REG3 {
+                               regulator-name = "vcc_ddr";
+                               regulator-always-on;
+                               regulator-boot-on;
+
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                               };
+                       };
+
+                       vcc_io: DCDC_REG4 {
+                               regulator-name = "vcc_io";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <3300000>;
+                               };
+                       };
+
+                       vcc_18: LDO_REG1 {
+                               regulator-name = "vcc_18";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1800000>;
+                               };
+                       };
+
+                       vcc18_emmc: LDO_REG2 {
+                               regulator-name = "vcc18_emmc";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1800000>;
+                               };
+                       };
+
+                       vdd_10: LDO_REG3 {
+                               regulator-name = "vdd_10";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <1000000>;
+
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1000000>;
+                               };
+                       };
+               };
+       };
+};
+
+&io_domains {
+       pmuio-supply = <&vcc_io>;
+       vccio1-supply = <&vcc_io>;
+       vccio2-supply = <&vcc18_emmc>;
+       vccio3-supply = <&vcc_io>;
+       vccio4-supply = <&vcc_io>;
+       vccio5-supply = <&vcc_io>;
+       vccio6-supply = <&vcc_io>;
+       status = "okay";
+};
+
+&pinctrl {
+       gmac2io {
+               eth_phy_reset_pin: eth-phy-reset-pin {
+                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+               };
+       };
+
+       leds {
+               lan_led_pin: lan-led-pin {
+                       rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               sys_led_pin: sys-led-pin {
+                       rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               wan_led_pin: wan-led-pin {
+                       rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       lan {
+               lan_vdd_pin: lan-vdd-pin {
+                       rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       pmic {
+               pmic_int_l: pmic-int-l {
+                       rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};
+
+&pwm2 {
+       status = "okay";
+};
+
+&sdmmc {
+       bus-width = <4>;
+       cap-sd-highspeed;
+       disable-wp;
+       pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, 
<&sdmmc0_bus4>;
+       pinctrl-names = "default";
+       vmmc-supply = <&vcc_sd>;
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <50000000>;
+       };
+};
+
+&tsadc {
+       rockchip,hw-tshut-mode = <0>;
+       rockchip,hw-tshut-polarity = <0>;
+       status = "okay";
+};
+
+&u2phy {
+       status = "okay";
+};
+
+&u2phy_host {
+       status = "okay";
+};
+
+&u2phy_otg {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
+&usb20_otg {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usbdrd3 {
+       dr_mode = "host";
+       status = "okay";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       /* Second port is for USB 3.0 */
+       rtl8153: device@2 {
+               compatible = "usbbda,8153";
+               reg = <2>;
+       };
+};
+
+&usb_host0_ehci {
+       status = "okay";
+};
+
+&usb_host0_ohci {
+       status = "okay";
+};
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS 
b/board/rockchip/evb_rk3328/MAINTAINERS
index 3c46613ab5..91dc6b58cf 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -18,6 +18,12 @@ F:      configs/nanopi-r2s-rk3328_defconfig
 F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
 F:      arch/arm/dts/rk3328-nanopi-r2s.dts
 
+ORANGEPI-R1-PLUS-RK3328
+M:      Tianling Shen <cns...@gmail.com>
+S:      Maintained
+F:      configs/orangepi-r1-plus-rk3328_defconfig
+F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+
 ROC-RK3328-CC
 M:      Loic Devulder <ldevul...@suse.com>
 M:      Chen-Yu Tsai <w...@csie.org>
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig 
b/configs/orangepi-r1-plus-rk3328_defconfig
new file mode 100644
index 0000000000..3f62f0588d
--- /dev/null
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_STACK=0x400000
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2000000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
-- 
2.40.1

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