> From: Bo Gan <ganbo...@gmail.com> > Sent: Monday, June 12, 2023 7:54 AM > To: u-boot@lists.denx.de > Cc: Bo Gan <ganbo...@gmail.com>; Rick Jian-Zhi Chen(陳建志) > <r...@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycli...@andestech.com>; Sean > Anderson <sean...@gmail.com>; Bin Meng <bmeng...@gmail.com>; Lukas Auer > <lukas.a...@aisec.fraunhofer.de> > Subject: [RESEND PATCH v2] riscv: setup per-hart stack earlier > > Harts need to use per-hart stack before any function call, even if that > function is a simple one. When the callee uses stack for register save/ > restore, especially RA, if nested call, concurrent access by multiple harts > on the same stack will cause data-race. > > This patch sets up SP before `board_init_f_alloc_reserve`. A side effect of > this is that the memory layout has changed as the following: > > +----------------+ +----------------+ <----- SPL_STACK/ > | ...... | | hart 0 stack | SYS_INIT_SP_ADDR > | malloc_base | +----------------+ > +----------------+ | hart 1 stack | > | GD | +----------------+ If not SMP, N=1 > +----------------+ | ...... | > | hart 0 stack | +----------------+ > +----------------+ ==> | hart N-1 stack| > | hart 1 stack | +----------------+ > +----------------+ | ...... | > | ...... | | malloc_base | > +----------------+ +----------------+ > | hart N-1 stack| | GD | > +----------------+ +----------------+ > | | | | > > Signed-off-by: Bo Gan <ganbo...@gmail.com> > Cc: Rick Chen <r...@andestech.com> > Cc: Leo <ycli...@andestech.com> > Cc: Sean Anderson <sean...@gmail.com> > Cc: Bin Meng <bmeng...@gmail.com> > Cc: Lukas Auer <lukas.a...@aisec.fraunhofer.de> > --- > > v2: > - Fixed macro CONFIG_SYS_INIT_SP_ADDR -> SYS_INIT_SP_ADDR > - Tested SPL with VisionFive 2 board > --- > arch/riscv/cpu/start.S | 37 ++++++++++++++++++++++++------------- > 1 file changed, 24 insertions(+), 13 deletions(-)
Reviewed-by: Rick Chen <r...@andestech.com>