> From: Bin Meng <bm...@tinylab.org>
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot@lists.denx.de
> Cc: Andre Przywara <andre.przyw...@arm.com>; Anup Patel
> <apa...@ventanamicro.com>; Jonas Schwöbel <jonasschwoe...@yahoo.de>; Kautuk
> Consul <kcon...@ventanamicro.com>; Leo Yu-Chi Liang(梁育齊)
> <ycli...@andestech.com>; Michael Walle <mich...@walle.cc>; Michal Simek
> <michal.si...@amd.com>; Nikita Shubin <n.shu...@yadro.com>; Rick Jian-Zhi
> Chen(陳建志) <r...@andestech.com>; Sean Anderson <sean...@gmail.com>; Sergei
> Antonov <sap...@gmail.com>; Simon Glass <s...@chromium.org>; Stefan
> Herbrechtsmeier <stefan.herbrechtsme...@weidmueller.com>; Svyatoslav Ryhel
> <clamo...@gmail.com>; Tianrui Wei <tianrui-...@outlook.com>; William Zhang
> <william.zh...@broadcom.com>; Yanhong Wang <yanhong.w...@starfivetech.com>;
> Peter Yu-Chien Lin(林宇謙) <peter...@andestech.com>
> Subject: [PATCH 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT
>
> As the RISC-V ACLINT specification is defined to be backward compatible with
> the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the
> source tree to be future-proof.
>
> Signed-off-by: Bin Meng <bm...@tinylab.org>
>
> ---
>
> MAINTAINERS | 2 +-
> arch/riscv/Kconfig | 8 ++++----
> arch/riscv/cpu/fu540/Kconfig | 2 +-
> arch/riscv/cpu/fu740/Kconfig | 2 +-
> arch/riscv/cpu/generic/Kconfig | 4 ++--
> arch/riscv/cpu/jh7110/Kconfig | 2 +-
> arch/riscv/include/asm/global_data.h | 4 ++--
> arch/riscv/include/asm/syscon.h | 2 +-
> arch/riscv/lib/Makefile | 2 +-
> .../lib/{sifive_clint.c => aclint_ipi.c} | 16 +++++++--------
> board/openpiton/riscv64/Kconfig | 2 +-
> board/sipeed/maix/Kconfig | 2 +-
> drivers/timer/Makefile | 2 +-
> ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +++++++++----------
> 14 files changed, 35 insertions(+), 35 deletions(-) rename
> arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (73%) rename
> drivers/timer/{sifive_clint_timer.c => riscv_aclint_timer.c} (75%)
Reviewed-by: Rick Chen <r...@andestech.com>
