> -----Original Message-----
> From: Chee, Tien Fong <tien.fong.c...@intel.com>
> Sent: Wednesday, 28 June, 2023 5:14 PM
> To: Lim, Jit Loon <jit.loon....@intel.com>; u-boot@lists.denx.de
> Cc: Jagan Teki <ja...@amarulasolutions.com>; Vignesh R
> <vigne...@ti.com>; Vasut, Marek <ma...@denx.de>; Simon
> <simon.k.r.goldschm...@gmail.com>; Hea, Kok Kiang
> <kok.kiang....@intel.com>; Lokanathan, Raaj <raaj.lokanat...@intel.com>;
> Maniyam, Dinesh <dinesh.mani...@intel.com>; Ng, Boon Khai
> <boon.khai...@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yusla...@intel.com>; Chong, Teik Heng
> <teik.heng.ch...@intel.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.za...@intel.com>; Tang, Sieu Mun
> <sieu.mun.t...@intel.com>
> Subject: RE: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new
> platform agilex5
>
> Hi Jit Loon,
>
> > -----Original Message-----
> > From: Lim, Jit Loon <jit.loon....@intel.com>
> > Sent: Wednesday, 21 June, 2023 11:16 AM
> > To: u-boot@lists.denx.de
> > Cc: Jagan Teki <ja...@amarulasolutions.com>; Vignesh R
> > <vigne...@ti.com>; Vasut, Marek <ma...@denx.de>; Simon
> > <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> > <tien.fong.c...@intel.com>; Hea, Kok Kiang <kok.kiang....@intel.com>;
> > Lokanathan, Raaj <raaj.lokanat...@intel.com>; Maniyam, Dinesh
> > <dinesh.mani...@intel.com>; Ng, Boon Khai <boon.khai...@intel.com>;
> > Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@intel.com>; Chong, Teik
> > Heng <teik.heng.ch...@intel.com>; Zamri, Muhammad Hazim Izzat
> > <muhammad.hazim.izzat.za...@intel.com>; Lim, Jit Loon
> > <jit.loon....@intel.com>; Tang, Sieu Mun <sieu.mun.t...@intel.com>
> > Subject: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new
> > platform
> > agilex5
> >
> > This is for new platform enablement for agilex5.
> > Add agilex5 dtsi and dts.
> > Update checkpatch error for stratix10.
>
> Why having checkpatch error for Stratix10?
> This should be in a separate patch.
>
> >
> > Signed-off-by: Jit Loon Lim <jit.loon....@intel.com>
> > ---
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 +++++++++++++
> > arch/arm/dts/socfpga_agilex5.dtsi | 634 ++++++++++++++++++
> > .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131 ++++
> > arch/arm/dts/socfpga_agilex5_socdk.dts | 165 +++++
> > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +-
> > arch/arm/dts/socfpga_soc64_u-boot.dtsi | 120 ++++
> > arch/arm/dts/socfpga_stratix10.dtsi | 0
> > .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0
> > arch/arm/dts/socfpga_stratix10_socdk.dts | 0
> > 10 files changed, 1534 insertions(+), 14 deletions(-) create mode
> > 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode
> > 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts
> > create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
> > mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi
> > mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-
> > boot.dtsi
> > mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> > 480269fa60..2e4bc556e1 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -456,6 +456,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) +=
> > thunderx-88xx.dtb
> >
> > dtb-$(CONFIG_ARCH_SOCFPGA) += \
> > socfpga_agilex_socdk.dtb \
> > + socfpga_agilex5_socdk.dtb \
> > socfpga_arria5_secu1.dtb \
> > socfpga_arria5_socdk.dtb \
> > socfpga_arria10_chameleonv3_270_2.dtb \
> > diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..6a1299901a
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> > @@ -0,0 +1,459 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */
> > +
> > +#include "socfpga_soc64_u-boot.dtsi"
> > +#include "socfpga_soc64_fit-u-boot.dtsi"
> > +
> > +/{
> > + memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + bootph-all;
> > + };
> > +
> > + soc {
> > + bootph-all;
> > +
> > + socfpga_secreg: socfpga-secreg {
> > + compatible = "intel,socfpga-secreg";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + bootph-all;
> > +
> > + /* DSU */
> > + i_ccu_caiu0@1c000000 {
> > + reg = <0x1c000000 0x00001000>;
> > + intel,offset-settings =
> > + /* CAIUAMIGR */
> > + <0x000003c0 0x00000003
> 0x0000001f>,
> > + /* CAIUMIFSR */
> > + <0x000003c4 0x00000000
> > 0x07070777>,
> > + /* DII1_MPFEREGS */
> > + <0x00000414 0x00018000 0xffffffff>,
> > + <0x00000418 0x00000000
> 0x000000ff>,
> > + <0x00000410 0xc0e00200
> 0xc1f03e1f>,
> > + /* DII2_GICREGS */
> > + <0x00000424 0x0001d000 0xffffffff>,
> > + <0x00000428 0x00000000
> 0x000000ff>,
> > + <0x00000420 0xc0800400
> 0xc1f03e1f>,
> > + /* NCAIU0_LWSOC2FPGA */
> > + <0x00000444 0x00020000 0xffffffff>,
> > + <0x00000448 0x00000000
> 0x000000ff>,
> > + <0x00000440 0xc1100006
> 0xc1f03e1f>,
> > + /* NCAIU0_SOC2FPGA_1G */
> > + <0x00000454 0x00040000 0xffffffff>,
> > + <0x00000458 0x00000000
> 0x000000ff>,
> > + <0x00000450 0xc1200006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_2G */
> > + <0x00000464 0x00080000 0xffffffff>,
> > + <0x00000468 0x00000000
> 0x000000ff>,
> > + <0x00000460 0x81300006
> 0xc1f03e1f>,
> > + /* NCAIU0_SOC2FPGA_16G */
> > + <0x00000474 0x00400000 0xffffffff>,
> > + <0x00000478 0x00000000
> 0x000000ff>,
> > + <0x00000470 0xc1600006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_30G */
> > + <0x00000484 0x00800000 0xffffffff>,
> > + <0x00000488 0x00000000
> 0x000000ff>,
> > + <0x00000480 0x81700006
> 0xc1f03e1f>,
> > + /* NCAIU0_SOC2FPGA_256G */
> > + <0x00000494 0x04000000 0xffffffff>,
> > + <0x00000498 0x00000000
> 0x000000ff>,
> > + <0x00000490 0xc1a00006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_480G */
> > + <0x000004a4 0x08000000 0xffffffff>,
> > + <0x000004a8 0x00000000
> 0x000000ff>,
> > + <0x000004a0 0x81b00006
> 0xc1f03e1f>;
> > + bootph-all;
> > + };
> > +
> > + /* FPGA2SOC */
> > + i_ccu_ncaiu0@1c001000 {
> > + reg = <0x1c001000 0x00001000>;
> > + intel,offset-settings =
> > + /* NCAIU0AMIGR */
> > + <0x000003c0 0x00000003
> 0x0000001f>,
> > + /* NCAIU0MIFSR */
> > + <0x000003c4 0x00000000
> > 0x07070777>,
> > + /* PSS */
> > + <0x00000404 0x00010000 0xffffffff>,
> > + <0x00000408 0x00000000
> 0x000000ff>,
> > + <0x00000400 0xC0F00000
> 0xc1f03e1f>,
> > + /* DII1_MPFEREGS */
> > + <0x00000414 0x00018000 0xffffffff>,
> > + <0x00000418 0x00000000
> 0x000000ff>,
> > + <0x00000410 0xc0e00200
> 0xc1f03e1f>,
> > + /* NCAIU0_LWSOC2FPGA */
> > + <0x00000444 0x00020000 0xffffffff>,
> > + <0x00000448 0x00000000
> 0x000000ff>,
> > + <0x00000440 0xc1100006
> 0xc1f03e1f>,
> > + /* NCAIU0_SOC2FPGA_1G */
> > + <0x00000454 0x00040000 0xffffffff>,
> > + <0x00000458 0x00000000
> 0x000000ff>,
> > + <0x00000450 0xc1200006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_2G */
> > + <0x00000464 0x00080000 0xffffffff>,
> > + <0x00000468 0x00000000
> 0x000000ff>,
> > + <0x00000460 0x81300006
> 0xc1f03e1f>,
> > + /* NCAIU0_SOC2FPGA_16G */
> > + <0x00000474 0x00400000 0xffffffff>,
> > + <0x00000478 0x00000000
> 0x000000ff>,
> > + <0x00000470 0xc1600006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_30G */
> > + <0x00000484 0x00800000 0xffffffff>,
> > + <0x00000488 0x00000000
> 0x000000ff>,
> > + <0x00000480 0x81700006
> 0xc1f03e1f>,
> > + /* NCAIU0_SOC2FPGA_256G */
> > + <0x00000494 0x04000000 0xffffffff>,
> > + <0x00000498 0x00000000
> 0x000000ff>,
> > + <0x00000490 0xc1a00006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_480G */
> > + <0x000004a4 0x08000000 0xffffffff>,
> > + <0x000004a8 0x00000000
> 0x000000ff>,
> > + <0x000004a0 0x81b00006
> 0xc1f03e1f>;
> > + bootph-all;
> > + };
> > +
> > + /* GIC_M */
> > + i_ccu_ncaiu1@1c002000 {
> > + reg = <0x1c002000 0x00001000>;
> > + intel,offset-settings =
> > + /* NCAIU1AMIGR */
> > + <0x000003c0 0x00000003
> 0x0000001f>,
> > + /* NCAIU1MIFSR */
> > + <0x000003c4 0x00000000
> > 0x07070777>,
> > + /* DMI_SDRAM_2G */
> > + <0x00000464 0x00080000 0xffffffff>,
> > + <0x00000468 0x00000000
> 0x000000ff>,
> > + <0x00000460 0x81300006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_30G */
> > + <0x00000484 0x00800000 0xffffffff>,
> > + <0x00000488 0x00000000
> 0x000000ff>,
> > + <0x00000480 0x81700006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_480G */
> > + <0x000004a4 0x08000000 0xffffffff>,
> > + <0x000004a8 0x00000000
> 0x000000ff>,
> > + <0x000004a0 0x81b00006
> 0xc1f03e1f>;
> > + bootph-all;
> > + };
> > +
> > + /* PSS NOC */
> > + i_ccu_ncaiu3@1c004000 {
> > + reg = <0x1c004000 0x00001000>;
> > + intel,offset-settings =
> > + /* NCAIU3AMIGR */
> > + <0x000003c0 0x00000003
> 0x0000001f>,
> > + /* NCAIU3MIFSR */
> > + <0x000003c4 0x00000000
> > 0x07070777>,
> > + /* DII1_MPFEREGS */
> > + <0x00000414 0x00018000 0xffffffff>,
> > + <0x00000418 0x00000000
> 0x000000ff>,
> > + <0x00000410 0xc0e00200
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_2G */
> > + <0x00000464 0x00080000 0xffffffff>,
> > + <0x00000468 0x00000000
> 0x000000ff>,
> > + <0x00000460 0x81300006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_30G */
> > + <0x00000484 0x00800000 0xffffffff>,
> > + <0x00000488 0x00000000
> 0x000000ff>,
> > + <0x00000480 0x81700006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_480G */
> > + <0x000004a4 0x08000000 0xffffffff>,
> > + <0x000004a8 0x00000000
> 0x000000ff>,
> > + <0x000004a0 0x81b00006
> 0xc1f03e1f>;
> > + bootph-all;
> > + };
> > +
> > + /* DCE0 */
> > + i_ccu_dce0@1c005000 {
> > + reg = <0x1c005000 0x00001000>;
> > + intel,offset-settings =
> > + /* DCEUAMIGR0 */
> > + <0x000003c0 0x00000003
> 0x0000001f>,
> > + /* DCEUMIFSR0 */
> > + <0x000003c4 0x00000000
> > 0x07070777>,
> > + /* DMI_SDRAM_2G */
> > + <0x00000464 0x00080000 0xffffffff>,
> > + <0x00000468 0x00000000
> 0x000000ff>,
> > + <0x00000460 0x81300006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_30G */
> > + <0x00000484 0x00800000 0xffffffff>,
> > + <0x00000488 0x00000000
> 0x000000ff>,
> > + <0x00000480 0x81700006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_480G */
> > + <0x000004a4 0x08000000 0xffffffff>,
> > + <0x000004a8 0x00000000
> 0x000000ff>,
> > + <0x000004a0 0x81b00006
> 0xc1f03e1f>;
> > + bootph-all;
> > + };
> > +
> > + /* DCE1 */
> > + i_ccu_dce1@1c006000 {
> > + reg = <0x1c006000 0x00001000>;
> > + intel,offset-settings =
> > + /* DCEUAMIGR1 */
> > + <0x000003c0 0x00000003
> 0x0000001f>,
> > + /* DCEUMIFSR1 */
> > + <0x000003c4 0x00000000
> > 0x07070777>,
> > + /* DMI_SDRAM_2G */
> > + <0x00000464 0x00080000 0xffffffff>,
> > + <0x00000468 0x00000000
> 0x000000ff>,
> > + <0x00000460 0x81300006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_30G */
> > + <0x00000484 0x00800000 0xffffffff>,
> > + <0x00000488 0x00000000
> 0x000000ff>,
> > + <0x00000480 0x81700006
> 0xc1f03e1f>,
> > + /* DMI_SDRAM_480G */
> > + <0x000004a4 0x08000000 0xffffffff>,
> > + <0x000004a8 0x00000000
> 0x000000ff>,
> > + <0x000004a0 0x81b00006
> 0xc1f03e1f>;
> > + bootph-all;
> > + };
> > +
> > + /* DMI0 */
> > + i_ccu_dmi0@1c007000 {
> > + reg = <0x1c007000 0x00001000>;
> > + intel,offset-settings =
> > + /* DMIUSMCTCR */
> > + <0x00000300 0x00000003
> > 0x00000003>;
> > + bootph-all;
> > + };
>
> Please exclude above secreg changes for now because this driver is not in
> mainline yet. You can submit another patch for these changes once the
> driver is accepted into mainline.
>
> > +
> > + /* DMI1 */
> > + i_ccu_dmi0@1c008000 {
> > + reg = <0x1c008000 0x00001000>;
> > + intel,offset-settings =
> > + /* DMIUSMCTCR */
> > + <0x00000300 0x00000003
> > 0x00000003>;
> > + bootph-all;
> > + };
> > +
> > + /* L4 peripherals firewall */
> > + noc_fw_l4_per@10d21000 {
> > + reg = <0x10d21000 0x0000008c>;
> > + intel,offset-settings =
> > + /* NAND */
> > + <0x00000000 0x01010001
> > 0x01010001>,
> > + /* USB0 */
> > + <0x0000000c 0x01010001
> > 0x01010001>,
> > + /* USB1 */
> > + <0x00000010 0x01010001
> > 0x01010001>,
> > + /* SPI_MAIN0 */
> > + <0x0000001c 0x01010301
> > 0x01010301>,
> > + /* SPI_MAIN1 */
> > + <0x00000020 0x01010301
> > 0x01010301>,
> > + /* SPI_SECONDARY0 */
> > + <0x00000024 0x01010301
> > 0x01010301>,
> > + /* SPI_SECONDARY1 */
> > + <0x00000028 0x01010301
> > 0x01010301>,
> > + /* EMAC0 */
> > + <0x0000002c 0x01010001
> > 0x01010001>,
> > + /* EMAC1 */
> > + <0x00000030 0x01010001
> > 0x01010001>,
> > + /* EMAC2 */
> > + <0x00000034 0x01010001
> > 0x01010001>,
> > + /* SDMMC */
> > + <0x00000040 0x01010001
> > 0x01010001>,
> > + /* GPIO0 */
> > + <0x00000044 0x01010301
> > 0x01010301>,
> > + /* GPIO1 */
> > + <0x00000048 0x01010301
> > 0x01010301>,
> > + /* I2C0 */
> > + <0x00000050 0x01010301
> > 0x01010301>,
> > + /* I2C1 */
> > + <0x00000054 0x01010301
> > 0x01010301>,
> > + /* I2C2 */
> > + <0x00000058 0x01010301
> > 0x01010301>,
> > + /* I2C3 */
> > + <0x0000005c 0x01010301
> > 0x01010301>,
> > + /* I2C4 */
> > + <0x00000060 0x01010301
> > 0x01010301>,
> > + /* SP_TIMER0 */
> > + <0x00000064 0x01010301
> > 0x01010301>,
> > + /* SP_TIMER1 */
> > + <0x00000068 0x01010301
> > 0x01010301>,
> > + /* UART0 */
> > + <0x0000006c 0x01010301
> > 0x01010301>,
> > + /* UART1 */
> > + <0x00000070 0x01010301
> > 0x01010301>,
> > + /* I3C0 */
> > + <0x00000074 0x01010301
> > 0x01010301>,
> > + /* I3C1 */
> > + <0x00000078 0x01010301
> > 0x01010301>,
> > + /* DMA0 */
> > + <0x0000007c 0x01010001
> > 0x01010001>,
> > + /* DMA1 */
> > + <0x00000080 0x01010001
> > 0x01010001>,
> > + /* COMBO_PHY */
> > + <0x00000084 0x01010001
> > 0x01010001>,
> > + /* NAND_SDMA */
> > + <0x00000088 0x01010301
> > 0x01010301>;
> > + bootph-all;
> > + };
> > +
> > + /* L4 system firewall */
> > + noc_fw_l4_sys@10d21100 {
> > + reg = <0x10d21100 0x00000098>;
> > + intel,offset-settings =
> > + /* DMA_ECC */
> > + <0x00000008 0x01010001
> > 0x01010001>,
> > + /* EMAC0RX_ECC */
> > + <0x0000000c 0x01010001
> > 0x01010001>,
> > + /* EMAC0TX_ECC */
> > + <0x00000010 0x01010001
> > 0x01010001>,
> > + /* EMAC1RX_ECC */
> > + <0x00000014 0x01010001
> > 0x01010001>,
> > + /* EMAC1TX_ECC */
> > + <0x00000018 0x01010001
> > 0x01010001>,
> > + /* EMAC2RX_ECC */
> > + <0x0000001c 0x01010001
> > 0x01010001>,
> > + /* EMAC2TX_ECC */
> > + <0x00000020 0x01010001
> > 0x01010001>,
> > + /* NAND_ECC */
> > + <0x0000002c 0x01010001
> > 0x01010001>,
> > + /* NAND_READ_ECC */
> > + <0x00000030 0x01010001
> > 0x01010001>,
> > + /* NAND_WRITE_ECC */
> > + <0x00000034 0x01010001
> > 0x01010001>,
> > + /* OCRAM_ECC */
> > + <0x00000038 0x01010001
> > 0x01010001>,
> > + /* SDMMC_ECC */
> > + <0x00000040 0x01010001
> > 0x01010001>,
> > + /* USB0_ECC */
> > + <0x00000044 0x01010001
> > 0x01010001>,
> > + /* USB1_CACHEECC */
> > + <0x00000048 0x01010001
> > 0x01010001>,
> > + /* CLOCK_MANAGER */
> > + <0x0000004c 0x01010001
> > 0x01010001>,
> > + /* IO_MANAGER */
> > + <0x00000054 0x01010001
> > 0x01010001>,
> > + /* RESET_MANAGER */
> > + <0x00000058 0x01010001
> > 0x01010001>,
> > + /* SYSTEM_MANAGER */
> > + <0x0000005c 0x01010001
> > 0x01010001>,
> > + /* OSC0_TIMER */
> > + <0x00000060 0x01010301
> > 0x01010301>,
> > + /* OSC1_TIMER0*/
> > + <0x00000064 0x01010301
> > 0x01010301>,
> > + /* WATCHDOG0 */
> > + <0x00000068 0x01010301
> > 0x01010301>,
> > + /* WATCHDOG1 */
> > + <0x0000006c 0x01010301
> > 0x01010301>,
> > + /* WATCHDOG2 */
> > + <0x00000070 0x01010301
> > 0x01010301>,
> > + /* WATCHDOG3 */
> > + <0x00000074 0x01010301
> > 0x01010301>,
> > + /* DAP */
> > + <0x00000078 0x03010001
> > 0x03010001>,
> > + /* WATCHDOG4 */
> > + <0x0000007c 0x01010301
> > 0x01010301>,
> > + /* POWER_MANAGER */
> > + <0x00000080 0x01010001
> > 0x01010001>,
> > + /* USB1_RXECC */
> > + <0x00000084 0x01010001
> > 0x01010001>,
> > + /* USB1_TXECC */
> > + <0x00000088 0x01010001
> > 0x01010001>,
> > + /* L4_NOC_PROBES */
> > + <0x00000090 0x01010001
> > 0x01010001>,
> > + /* L4_NOC_QOS */
> > + <0x00000094 0x01010001
> > 0x01010001>;
> > + bootph-all;
> > + };
> > +
> > + /* Light weight SoC2FPGA */
> > + noc_fw_lwsoc2fpga@10d21300 {
> > + reg = <0x10d21300 0x0000004>;
> > + intel,offset-settings =
> > + /* LWSOC2FPGA_CSR */
> > + <0x00000000 0x0ffe0301>;
> > + bootph-all;
> > + };
> > +
> > + /* SoC2FPGA */
> > + noc_fw_soc2fpga@10d21200 {
> > + reg = <0x10d21200 0x0000004>;
> > + intel,offset-settings =
> > + /* SOC2FPGA_CSR */
> > + <0x00000000 0x0ffe0301 0x0ffe0301>;
> > + bootph-all;
> > + };
> > +
> > + /* TCU */
> > + noc_fw_tcu@10d21400 {
> > + reg = <0x10d21400 0x0000004>;
> > + intel,offset-settings =
> > + /* TCU_CSR */
> > + <0x00000000 0x01010001
> > 0x01010001>;
> > + bootph-all;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&clkmgr {
> > + bootph-all;
> > +};
> > +
> > +&i2c0 {
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c1 {
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c2 {
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c3 {
> > + reset-names = "i2c";
> > +};
> > +
> > +&mmc {
> > + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; };
> > +
> > +&porta {
> > + bank-name = "porta";
> > +};
> > +
> > +&portb {
> > + bank-name = "portb";
> > +};
> > +
> > +&qspi {
> > + bootph-all;
> > +};
> > +
> > +&rst {
> > + compatible = "altr,rst-mgr";
> > + altr,modrst-offset = <0x24>;
> > + bootph-all;
> > +};
> > +
> > +&sdr {
> > + compatible = "intel,sdr-ctl-agilex5";
> > + reg = <0x18000000 0x400000>,
> > + <0x18400000 0x400000>,
> > + <0x18800000 0x400000>;
> > + resets = <&rst DDRSCH_RESET>;
> > + bootph-all;
> > +};
> > +
> > +&sysmgr {
> > + compatible = "altr,sys-mgr", "syscon";
> > + bootph-all;
> > +};
> > +
> > +&uart0 {
> > + bootph-all;
> > +};
> > +
> > +&watchdog0 {
> > + bootph-all;
> > +};
> > diff --git a/arch/arm/dts/socfpga_agilex5.dtsi
> > b/arch/arm/dts/socfpga_agilex5.dtsi
> > new file mode 100644
> > index 0000000000..f445bc04ad
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_agilex5.dtsi
> > @@ -0,0 +1,634 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2022, Intel Corporation */
> > +
> > +/dts-v1/;
> > +#include <dt-bindings/reset/altr,rst-mgr-agx5.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/clock/agilex5-clock.h>
> > +
> > +/ {
> > + compatible = "intel,socfpga-agilex";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + service_reserved: svcbuffer@0 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x0 0x0 0x0 0x1000000>;
> > + alignment = <0x1000>;
> > + no-map;
> > + };
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,cortex-a55";
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + reg = <0x0>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + compatible = "arm,cortex-a55";
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + reg = <0x1>;
> > + };
> > +
> > + cpu2: cpu@2 {
> > + compatible = "arm,cortex-a76";
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + reg = <0x2>;
> > + };
> > +
> > + cpu3: cpu@3 {
> > + compatible = "arm,cortex-a76";
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + reg = <0x3>;
> > + };
> > + };
> > +
> > + pmu {
> > + compatible = "arm,armv8-pmuv3";
> > + interrupts = <0 170 4>,
> > + <0 171 4>,
> > + <0 172 4>,
> > + <0 173 4>;
> > + interrupt-affinity = <&cpu0>,
> > + <&cpu1>,
> > + <&cpu2>,
> > + <&cpu3>;
> > + interrupt-parent = <&intc>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + intc: intc@fffc1000 {
> > + compatible = "arm,gic-400", "arm,cortex-a15-gic";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x0 0x1d000000 0x0 0x10000>;
> > + };
> > +
> > + soc {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "simple-bus";
> > + device_type = "soc";
> > + interrupt-parent = <&intc>;
> > + ranges = <0 0 0 0xffffffff>;
> > +
> > + base_fpga_region {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x1>;
> > + compatible = "fpga-region";
> > + fpga-mgr = <&fpga_mgr>;
> > + };
> > +
> > + clkmgr: clock-controller@10d10000 {
> > + compatible = "intel,agilex5-clkmgr";
> > + reg = <0x10d10000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + clocks {
> > + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + };
> > +
> > + cb_intosc_ls_clk: cb-intosc-ls-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + };
> > +
> > + f2s_free_clk: f2s-free-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + };
> > +
> > + osc1: osc1 {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + };
> > +
> > + qspi_clk: qspi-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <200000000>;
> > + };
> > + };
> > + gmac0: ethernet@10810000 {
> > + compatible = "altr,socfpga-stmmac", "snps,dwmac-
> > 3.74a", "snps,dwmac";
> > + reg = <0x10810000 0x3500>;
> > + interrupts = <0 90 4>;
> > + interrupt-names = "macirq";
> > + mac-address = [00 00 00 00 00 00];
> > + resets = <&rst EMAC0_RESET>, <&rst
> > EMAC0_OCP_RESET>;
> > + reset-names = "stmmaceth", "stmmaceth-ocp";
> > + tx-fifo-depth = <16384>;
> > + rx-fifo-depth = <16384>;
> > + snps,multicast-filter-bins = <256>;
> > + iommus = <&smmu 1>;
> > + altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> > + clocks = <&clkmgr AGILEX5_EMAC0_CLK>;
> > + clock-names = "stmmaceth";
> > + status = "disabled";
> > + };
> > +
> > + gmac1: ethernet@10820000 {
> > + compatible = "altr,socfpga-stmmac", "snps,dwmac-
> > 3.74a", "snps,dwmac";
> > + reg = <0x10820000 0x3500>;
> > + interrupts = <0 91 4>;
> > + interrupt-names = "macirq";
> > + mac-address = [00 00 00 00 00 00];
> > + resets = <&rst EMAC1_RESET>, <&rst
> > EMAC1_OCP_RESET>;
> > + reset-names = "stmmaceth", "stmmaceth-ocp";
> > + tx-fifo-depth = <16384>;
> > + rx-fifo-depth = <16384>;
> > + snps,multicast-filter-bins = <256>;
> > + iommus = <&smmu 2>;
> > + altr,sysmgr-syscon = <&sysmgr 0x48 8>;
> > + clocks = <&clkmgr AGILEX5_EMAC1_CLK>;
> > + clock-names = "stmmaceth";
> > + status = "disabled";
> > + };
> > +
> > + gmac2: ethernet@10830000 {
> > + compatible = "altr,socfpga-stmmac", "snps,dwmac-
> > 3.74a", "snps,dwmac";
> > + reg = <0x10830000 0x3500>;
> > + interrupts = <0 92 4>;
> > + interrupt-names = "macirq";
> > + mac-address = [00 00 00 00 00 00];
> > + resets = <&rst EMAC2_RESET>, <&rst
> > EMAC2_OCP_RESET>;
> > + reset-names = "stmmaceth", "stmmaceth-ocp";
> > + tx-fifo-depth = <16384>;
> > + rx-fifo-depth = <16384>;
> > + snps,multicast-filter-bins = <256>;
> > + iommus = <&smmu 3>;
> > + altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
> > + clocks = <&clkmgr AGILEX5_EMAC2_CLK>;
> > + clock-names = "stmmaceth";
> > + status = "disabled";
> > + };
> > +
> > + gpio0: gpio@10c03200 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dw-apb-gpio";
> > + reg = <0x10c03200 0x80>;
> > + resets = <&rst GPIO0_RESET>;
> > + status = "disabled";
> > +
> > + porta: gpio-controller@0 {
> > + compatible = "snps,dw-apb-gpio-port";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + snps,nr-gpios = <24>;
> > + reg = <0>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupts = <0 110 4>;
> > + };
> > + };
> > +
> > + gpio1: gpio@10c03300 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dw-apb-gpio";
> > + reg = <0x10c03300 0x80>;
> > + resets = <&rst GPIO1_RESET>;
> > + status = "disabled";
> > +
> > + portb: gpio-controller@0 {
> > + compatible = "snps,dw-apb-gpio-port";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + snps,nr-gpios = <24>;
> > + reg = <0>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupts = <0 111 4>;
> > + };
> > + };
> > +
> > + i2c0: i2c@10c02800 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,designware-i2c";
> > + reg = <0x10c02800 0x100>;
> > + interrupts = <0 103 4>;
> > + resets = <&rst I2C0_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c@10c02900 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,designware-i2c";
> > + reg = <0x10c02900 0x100>;
> > + interrupts = <0 104 4>;
> > + resets = <&rst I2C1_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + i2c2: i2c@10c02a00 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,designware-i2c";
> > + reg = <0x10c02a00 0x100>;
> > + interrupts = <0 105 4>;
> > + resets = <&rst I2C2_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + i2c3: i2c@10c02b00 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,designware-i2c";
> > + reg = <0x10c02b00 0x100>;
> > + interrupts = <0 106 4>;
> > + resets = <&rst I2C3_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + i2c4: i2c@10c02c00 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,designware-i2c";
> > + reg = <0x10c02c00 0x100>;
> > + interrupts = <0 107 4>;
> > + resets = <&rst I2C4_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + combophy0: combophy@0 {
> > + #phy-cells = <0>;
> > + phy-type = <1>;
> > + compatible = "cdns,combophy";
> > + reg = <0x10808000 0x1000>;
> > + resets = <&rst COMBOPHY_RESET>;
> > + reset-names = "reset";
> > + status = "disabled";
> > + };
> > +
> > + mmc: mmc0@10808000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "cdns,sd4hc";
> > + reg = <0x10808000 0x1000>;
> > + interrupts = <0 96 4>;
> > + phys = <&combophy0>;
> > + phy-names = "combo-phy";
> > + clocks = <&clkmgr AGILEX5_L4_MP_CLK>,
> > + <&clkmgr AGILEX5_SDMMC_CLK>;
> > + clock-names = "biu", "ciu";
> > + fifo-depth = <0x800>;
> > + resets = <&rst SDMMC_RESET>;
> > + reset-names = "reset";
> > + iommus = <&smmu 5>;
> > + status = "disabled";
> > + };
> > +
> > + nand: nand@10b80000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "altr,socfpga-denali-nand";
> > + reg = <0x10b80000 0x1038>,
> > + <0xffb80000 0x1000>;
> > + reg-names = "nand_data", "denali_reg";
> > + interrupts = <0 97 4>;
> > + clocks = <&clkmgr AGILEX5_NAND_CLK>,
> > + <&clkmgr AGILEX5_NAND_X_CLK>;
> > + clock-names = "nand", "nand_x";
> > + resets = <&rst NAND_RESET>, <&rst
> > NAND_OCP_RESET>;
> > + status = "disabled";
> > + };
> > +
> > + ocram: sram@00000000 {
> > + compatible = "mmio-sram";
> > + reg = <0x00000000 0x200000>;
> > + };
> > +
> > + rst: rstmgr@10d11000 {
> > + #reset-cells = <1>;
> > + compatible = "altr,stratix10-rst-mgr";
> > + reg = <0x10d11000 0x1000>;
> > + };
> > +
> > + smmu: iommu@16000000 {
> > + compatible = "arm,mmu-500", "arm,smmu-v2";
> > + reg = <0x16000000 0x40000>;
> > + #global-interrupts = <2>;
> > + #iommu-cells = <1>;
> > + interrupt-parent = <&intc>;
> > + interrupts = <0 128 4>, /* Global Secure Fault */
> > + <0 129 4>, /* Global Non-secure Fault */
> > + /* Non-secure Context Interrupts (32) */
> > + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
> > + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
> > + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
> > + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
> > + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
> > + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
> > + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
> > + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
> > + stream-match-mask = <0x7ff0>;
> > + status = "disabled";
> > + };
> > +
> > + spi0: spi@10da4000 {
> > + compatible = "intel,agilex-spi",
> > + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-
> > ssi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x10da4000 0x1000>;
> > + interrupts = <0 99 4>;
> > + resets = <&rst SPIM0_RESET>;
> > + reg-io-width = <4>;
> > + num-cs = <4>;
> > + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + spi1: spi@10da5000 {
> > + compatible = "intel,agilex-spi",
> > + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-
> > ssi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x10da5000 0x1000>;
> > + interrupts = <0 100 4>;
> > + resets = <&rst SPIM1_RESET>;
> > + reg-io-width = <4>;
> > + num-cs = <4>;
> > + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + sysmgr: sysmgr@10d12000 {
> > + compatible = "altr,sys-mgr-s10","altr,sys-mgr";
> > + reg = <0x10d12000 0x500>;
> > + };
> > +
> > + /* Local timer */
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <1 13 0xf08>,
> > + <1 14 0xf08>,
> > + <1 11 0xf08>,
> > + <1 10 0xf08>;
> > + };
> > +
> > + timer0: timer0@10c03000 {
> > + compatible = "snps,dw-apb-timer";
> > + interrupts = <0 113 4>;
> > + reg = <0x10c03000 0x100>;
> > + resets = <&rst SPTIMER0_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + clock-names = "timer";
> > + status = "disabled";
> > + };
> > +
> > + timer1: timer1@10c03100 {
> > + compatible = "snps,dw-apb-timer";
> > + interrupts = <0 114 4>;
> > + reg = <0x10c03100 0x100>;
> > + resets = <&rst SPTIMER1_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + clock-names = "timer";
> > + status = "disabled";
> > + };
> > +
> > + timer2: timer2@10d00000 {
> > + compatible = "snps,dw-apb-timer";
> > + interrupts = <0 115 4>;
> > + reg = <0x10d00000 0x100>;
> > + resets = <&rst L4SYSTIMER0_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
> > + clock-names = "timer";
> > + status = "disabled";
> > + };
> > +
> > + timer3: timer3@10d00100 {
> > + compatible = "snps,dw-apb-timer";
> > + interrupts = <0 116 4>;
> > + reg = <0x10d00100 0x100>;
> > + resets = <&rst L4SYSTIMER1_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
> > + clock-names = "timer";
> > + status = "disabled";
> > + };
> > +
> > + uart0: serial0@10c02000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x10c02000 0x100>;
> > + interrupts = <0 108 4>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + resets = <&rst UART0_RESET>;
> > + status = "disabled";
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + uart1: serial1@10c02100 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x10c02100 0x100>;
> > + interrupts = <0 109 4>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + resets = <&rst UART1_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + usbphy0: usbphy@0 {
> > + #phy-cells = <0>;
> > + compatible = "usb-nop-xceiv";
> > + clocks = <&clkmgr AGILEX5_USB_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + usb0: usb@10b00000 {
> > + compatible = "snps,dwc2";
> > + reg = <0x10b00000 0x40000>;
> > + interrupts = <0 93 4>;
> > + phys = <&usbphy0>;
> > + phy-names = "usb2-phy";
> > + resets = <&rst USB0_RESET>, <&rst
> > USB0_OCP_RESET>;
> > + reset-names = "dwc2", "dwc2-ecc";
> > + clocks = <&clkmgr AGILEX5_USB_CLK>;
> > + iommus = <&smmu 6>;
> > + status = "disabled";
> > + };
> > +
> > + usb31: usb31@11000000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x11000000 0x100000>;
> > + resets = <&rst USB1_RESET>;
> > + phys = <&usbphy0>, <&usbphy0>;
> > + phy-names = "usb2-phy", "usb3-phy";
> > + dr_mode = "host";
> > + maximum-speed = "super-speed";
> > + snps,dis_u2_susphy_quirk;
> > + status = "disabled";
> > + };
> > +
> > + watchdog0: watchdog@10d00200 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x10d00200 0x100>;
> > + interrupts = <0 117 4>;
> > + resets = <&rst WATCHDOG0_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + watchdog1: watchdog@10d00300 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x10d00300 0x100>;
> > + interrupts = <0 118 4>;
> > + resets = <&rst WATCHDOG1_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + watchdog2: watchdog@10d00400 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x10d00400 0x100>;
> > + interrupts = <0 125 4>;
> > + resets = <&rst WATCHDOG2_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + watchdog3: watchdog@10d00500 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x10d00500 0x100>;
> > + interrupts = <0 126 4>;
> > + resets = <&rst WATCHDOG3_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + watchdog4: watchdog@10d00600 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x10d00600 0x100>;
> > + interrupts = <0 175 4>;
> > + resets = <&rst WATCHDOG4_RESET>;
> > + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
> > + status = "disabled";
> > + };
> > +
> > + sdr: sdr@10d21000 {
> > + compatible = "altr,sdr-ctl", "syscon";
> > + reg = <0x10d21000 0xc0>;
> > + };
> > +
> > + /* TODO: Update the ECC registers */
> > + eccmgr {
> > + compatible = "altr,socfpga-s10-ecc-manager",
> > + "altr,socfpga-a10-ecc-manager";
> > + altr,sysmgr-syscon = <&sysmgr>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + interrupts = <0 15 4>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + ranges;
> > +
> > + sdramedac {
> > + compatible = "altr,sdram-edac-s10";
> > + altr,sdr-syscon = <&sdr>;
> > + interrupts = <16 4>;
> > + };
> > +
> > + ocram-ecc@ff8cc000 {
> > + compatible = "altr,socfpga-s10-ocram-ecc",
> > + "altr,socfpga-a10-ocram-ecc";
> > + reg = <0xff8cc000 0x100>;
> > + altr,ecc-parent = <&ocram>;
> > + interrupts = <1 4>;
> > + };
> > +
> > + usb0-ecc@ff8c4000 {
> > + compatible = "altr,socfpga-s10-usb-ecc",
> > + "altr,socfpga-usb-ecc";
> > + reg = <0xff8c4000 0x100>;
> > + altr,ecc-parent = <&usb0>;
> > + interrupts = <2 4>;
> > + };
> > +
> > + emac0-rx-ecc@ff8c0000 {
> > + compatible = "altr,socfpga-s10-eth-mac-ecc",
> > + "altr,socfpga-eth-mac-ecc";
> > + reg = <0xff8c0000 0x100>;
> > + altr,ecc-parent = <&gmac0>;
> > + interrupts = <4 4>;
> > + };
> > +
> > + emac0-tx-ecc@ff8c0400 {
> > + compatible = "altr,socfpga-s10-eth-mac-ecc",
> > + "altr,socfpga-eth-mac-ecc";
> > + reg = <0xff8c0400 0x100>;
> > + altr,ecc-parent = <&gmac0>;
> > + interrupts = <5 4>;
> > + };
> > +
> > + sdmmca-ecc@ff8c8c00 {
> > + compatible = "altr,socfpga-s10-sdmmc-ecc",
> > + "altr,socfpga-sdmmc-ecc";
> > + reg = <0xff8c8c00 0x100>;
> > + altr,ecc-parent = <&mmc>;
> > + interrupts = <14 4>,
> > + <15 4>;
> > + };
> > + };
> > +
> > + /* QSPI address not available yet */
> > + qspi: spi@108d2000 {
> > + compatible = "cdns,qspi-nor";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x108d2000 0x100>,
> > + <0x10900000 0x100000>;
> > + interrupts = <0 3 4>;
> > + cdns,fifo-depth = <128>;
> > + cdns,fifo-width = <4>;
> > + cdns,trigger-address = <0x00000000>;
> > + clocks = <&qspi_clk>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + firmware {
> > + svc {
> > + compatible = "intel,stratix10-svc";
> > + method = "smc";
> > + memory-region = <&service_reserved>;
> > +
> > + fpga_mgr: fpga-mgr {
> > + compatible = "intel,stratix10-soc-
> > fpga-mgr";
> > + };
> > + };
> > + };
> > + };
> > +};
> > diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..ad170353f8
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
> > @@ -0,0 +1,131 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2022 Intel Corporation <www.intel.com> */
> > +
> > +#include "socfpga_agilex5-u-boot.dtsi"
> > +
> > +/{
> > + aliases {
> > + spi0 = &qspi;
> > + freeze_br0 = &freeze_controller;
> > + };
> > +
> > + soc {
> > + freeze_controller: freeze_controller@f9000450 {
> > + compatible = "altr,freeze-bridge-controller";
> > + reg = <0xf9000450 0x00000010>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + memory {
> > + /* 2GB on Simics*/
> > + reg = <0 0x80000000 0 0x80000000>;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + u-boot,spl-boot-order = &mmc,&flash0,"/memory";
> > + };
> > +};
> > +
> > +&flash0 {
> > + compatible = "jedec,spi-nor";
> > + spi-tx-bus-width = <4>;
> > + spi-rx-bus-width = <4>;
> > + bootph-all;
> > +};
> > +
> > +&nand {
> > + status = "okay";
> > + nand-bus-width = <16>;
> > + bootph-all;
> > +};
> > +
> > +&mmc {
> > + status = "okay";
> > + bus-width = <4>;
> > + sd-uhs-sdr50;
> > + cap-mmc-highspeed;
> > + bootph-all;
> > +};
> > +
> > +&combophy0 {
> > + status = "okay";
> > + bootph-all;
> > + cdns,phy-use-ext-lpbk-dqs = <1>;
> > + cdns,phy-use-lpbk-dqs = <1>;
> > + cdns,phy-use-phony-dqs = <1>;
> > + cdns,phy-use-phony-dqs-cmd = <1>;
> > + cdns,phy-io-mask-always-on = <0>;
> > + cdns,phy-io-mask-end = <5>;
> > + cdns,phy-io-mask-start = <0>;
> > + cdns,phy-data-select-oe-end = <1>;
> > + cdns,phy-sync-method = <1>;
> > + cdns,phy-sw-half-cycle-shift = <0>;
> > + cdns,phy-rd-del-sel = <52>;
> > + cdns,phy-underrun-suppress = <1>;
> > + cdns,phy-gate-cfg-always-on = <1>;
> > + cdns,phy-param-dll-bypass-mode = <1>;
> > + cdns,phy-param-phase-detect-sel = <2>;
> > + cdns,phy-param-dll-start-point = <254>;
> > + cdns,phy-read-dqs-cmd-delay = <0>;
> > + cdns,phy-clk-wrdqs-delay = <0>;
> > + cdns,phy-clk-wr-delay = <0>;
> > + cdns,phy-read-dqs-delay = <0>;
> > + cdns,phy-phony-dqs-timing = <0>;
> > + cdns,hrs09-rddata-en = <1>;
> > + cdns,hrs09-rdcmd-en = <1>;
> > + cdns,hrs09-extended-wr-mode = <1>;
> > + cdns,hrs09-extended-rd-mode = <1>;
> > + cdns,hrs10-hcsdclkadj = <3>;
> > + cdns,hrs16-wrdata1-sdclk-dly = <0>;
> > + cdns,hrs16-wrdata0-sdclk-dly = <0>;
> > + cdns,hrs16-wrcmd1-sdclk-dly = <0>;
> > + cdns,hrs16-wrcmd0-sdclk-dly = <0>;
> > + cdns,hrs16-wrdata1-dly = <0>;
> > + cdns,hrs16-wrdata0-dly = <0>;
> > + cdns,hrs16-wrcmd1-dly = <0>;
> > + cdns,hrs16-wrcmd0-dly = <0>;
> > + cdns,hrs07-rw-compensate = <10>;
> > + cdns,hrs07-idelay-val = <0>;
> > +};
> > +
> > +&qspi {
> > + status = "okay";
> > +};
> > +
> > +&timer0 {
> > + bootph-all;
> > +};
> > +
> > +&timer1 {
> > + bootph-all;
> > +};
> > +
> > +&timer2 {
> > + bootph-all;
> > +};
> > +
> > +&timer3 {
> > + bootph-all;
> > +};
> > +
> > +&watchdog0 {
> > + bootph-all;
> > +};
> > +
> > +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
> > +&fdt_0_blob {
> > + filename = "arch/arm/dts/socfpga_agilex5_socdk.dtb";
> > +};
> > +
> > +/* To add NAND dtb when ready in future */
> > +
> > +&binman {
> > + /delete-node/ kernel;
> > +};
> > +#endif
> > diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts
> > b/arch/arm/dts/socfpga_agilex5_socdk.dts
> > new file mode 100644
> > index 0000000000..1a39426561
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
> > @@ -0,0 +1,165 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019-2022, Intel Corporation */ #include
> > +"socfpga_agilex5.dtsi"
> > +
> > +/ {
> > + model = "SoCFPGA Agilex5 SoCDK";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + leds {
> > + compatible = "gpio-leds";
> > + hps0 {
> > + label = "hps_led0";
> > + gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
> > + };
> > +
> > + hps1 {
> > + label = "hps_led1";
> > + gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
> > + };
> > +
> > + hps2 {
> > + label = "hps_led2";
> > + gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
> > + };
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + /* We expect the bootloader to fill in the reg */
> > + reg = <0 0 0 0>;
> > + };
> > +
> > + soc {
> > + clocks {
> > + osc1 {
> > + clock-frequency = <25000000>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&gpio0 {
> > + status = "okay";
> > +};
> > +
> > +&gpio1 {
> > + status = "okay";
> > +};
> > +
> > +&i2c0 {
> > + status = "okay";
> > +};
> > +
> > +&i2c1 {
> > + status = "okay";
> > +};
> > +
> > +&mmc {
> > + status = "okay";
> > +};
> > +
> > +&combophy0 {
> > + status = "okay";
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > +
> > +&usbphy0 {
> > + status = "okay";
> > +};
> > +
> > +&usb0 {
> > + status = "okay";
> > + disable-over-current;
> > +};
> > +
> > +&usb31 {
> > + status = "okay";
> > +};
> > +
> > +&watchdog0 {
> > + status = "okay";
> > +};
> > +
> > +&watchdog1 {
> > + status = "okay";
> > +};
> > +
> > +&watchdog2 {
> > + status = "okay";
> > +};
> > +
> > +&watchdog3 {
> > + status = "okay";
> > +};
> > +
> > +&watchdog4 {
> > + status = "okay";
> > +};
> > +
> > +&timer0 {
> > + status = "okay";
> > +};
> > +
> > +&timer1 {
> > + status = "okay";
> > +};
> > +
> > +&timer2 {
> > + status = "okay";
> > +};
> > +
> > +&timer3 {
> > + status = "okay";
> > +};
> > +
> > +&spi0 {
> > + status = "okay";
> > +};
> > +
> > +&spi1 {
> > + status = "okay";
> > +};
> > +
> > +&qspi {
> > + flash0: flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "mt25qu02g";
> > + reg = <0>;
> > + spi-max-frequency = <100000000>;
> > +
> > + m25p,fast-read;
> > + cdns,page-size = <256>;
> > + cdns,block-size = <16>;
> > + cdns,read-delay = <1>;
> > + cdns,tshsl-ns = <50>;
> > + cdns,tsd2d-ns = <50>;
> > + cdns,tchsh-ns = <4>;
> > + cdns,tslch-ns = <4>;
> > +
> > + partitions {
> > + compatible = "fixed-partitions";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + qspi_boot: partition@0 {
> > + label = "Boot and fpga data";
> > + reg = <0x0 0x034B0000>;
> > + };
> > +
> > + qspi_rootfs: partition@34B0000 {
> > + label = "Root Filesystem - JFFS2";
> > + reg = <0x034B0000 0x0EB50000>;
> > + };
> > + };
> > + };
> > +};
> > diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> > b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> > index 84b91e8df0..1ca721f070 100644
> > --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> > +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> > @@ -2,7 +2,7 @@
> > /*
> > * U-Boot additions
> > *
> > - * Copyright (C) 2020 Intel Corporation <www.intel.com>
> > + * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
> > */
> >
> > #if defined(CONFIG_FIT)
> > @@ -21,14 +21,18 @@
> > description = "FIT with firmware and bootloader";
> > #address-cells = <1>;
> >
> > - images {
> > + images: images {
> > uboot {
> > description = "U-Boot SoC64";
> > type = "standalone";
> > os = "U-Boot";
> > arch = "arm64";
> > compression = "none";
> > + #if
> > IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
> > + load = <0x80200000>;
> > + #else
> > load = <0x00200000>;
> > + #endif
> > uboot_blob: blob-ext {
> > filename = "u-boot-
> > nodtb.bin";
> > };
> > @@ -43,8 +47,13 @@
> > os = "arm-trusted-firmware";
> > arch = "arm64";
> > compression = "none";
> > + #if
> > IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
> > + load = <0x80000000>;
> > + entry = <0x80000000>;
> > + #else
> > load = <0x00001000>;
> > entry = <0x00001000>;
> > + #endif
> > atf_blob: blob-ext {
> > filename = "bl31.bin";
> > };
> > @@ -53,11 +62,11 @@
> > };
> > };
> >
> > - fdt {
> > - description = "U-Boot SoC64 flat
> > device-tree";
> > + fdt-0 {
> > + description = "socfpga_socdk";
> > type = "flat_dt";
> > compression = "none";
> > - uboot_fdt_blob: blob-ext {
> > + fdt_0_blob: blob-ext {
> > filename = "u-boot.dtb";
> > };
> > hash {
> > @@ -66,17 +75,18 @@
> > };
> > };
> >
> > - configurations {
> > - default = "conf";
> > - conf {
> > - description = "Intel SoC64 FPGA";
> > + board_config: configurations {
> > + default = "board-0";
> > +
> > + board-0 {
> > + description = "board_0";
> > firmware = "atf";
> > loadables = "uboot";
> > - fdt = "fdt";
> > + fdt = "fdt-0";
> > signature {
> > algo = "crc32";
> > key-name-hint = "dev";
> > - sign-images = "atf", "fdt",
> > "uboot";
> > + sign-images = "atf", "uboot",
> > "fdt-0";
> > };
> > };
> > };
> > @@ -96,8 +106,8 @@
> > arch = "arm64";
> > os = "linux";
> > compression = "none";
> > - load = <0x4080000>;
> > - entry = <0x4080000>;
> > + load = <0x6000000>;
> > + entry = <0x6000000>;
> > kernel_blob: blob-ext {
> > filename = "Image";
> > };
> > @@ -146,7 +156,7 @@
> > filename = "signed-bl31.bin";
> > };
> >
> > -&uboot_fdt_blob {
> > +&fdt_0_blob {
> > filename = "signed-u-boot.dtb";
> > };
> >
> > diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi
> > b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
> > new file mode 100644
> > index 0000000000..add9890de3
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
> > @@ -0,0 +1,120 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2021-2022 Intel Corporation <www.intel.com> */
> > +
> > +/ {
> > + soc {
> > + socfpga_secreg: socfpga-secreg {
> > + compatible = "intel,socfpga-secreg";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + bootph-all;
> > +
> > + i_sys_mgr_core@ffd12000 {
> > + reg = <0xffd12000 0x00000230>;
> > + intel,offset-settings =
> > + /* Enable non-secure interface to
> > DMA */
> > + <0x00000020 0xff010000 0xff010011>,
> > + /* Enable non-secure interface to
> > DMA periph */
> > + <0x00000024 0xffffffff 0xffffffff>;
> > + bootph-all;
> > + };
> > +
> > + noc_fw_l4_per_l4_per_scr@ffd21000 {
> > + reg = <0xffd21000 0x00000074>;
> > + intel,offset-settings =
> > + /* Disable L4 periphs firewall */
> > + <0x00000000 0x01010001
> > 0x01010001>,
> > + <0x00000004 0x01010001
> > 0x01010001>,
> > + <0x0000000c 0x01010001
> > 0x01010001>,
> > + <0x00000010 0x01010001
> > 0x01010001>,
> > + <0x0000001c 0x01010001
> > 0x01010101>,
> > + <0x00000020 0x01010001
> > 0x01010101>,
> > + <0x00000024 0x01010001
> > 0x01010101>,
> > + <0x00000028 0x01010001
> > 0x01010101>,
> > + <0x0000002c 0x01010001
> > 0x01010001>,
> > + <0x00000030 0x01010001
> > 0x01010001>,
> > + <0x00000034 0x01010001
> > 0x01010001>,
> > + <0x00000040 0x01010001
> > 0x01010001>,
> > + <0x00000044 0x01010001
> > 0x01010101>,
> > + <0x00000048 0x01010001
> > 0x01010101>,
> > + <0x00000050 0x01010001
> > 0x01010101>,
> > + <0x00000054 0x01010001
> > 0x01010101>,
> > + <0x00000058 0x01010001
> > 0x01010101>,
> > + <0x0000005c 0x01010001
> > 0x01010101>,
> > + <0x00000060 0x01010001
> > 0x01010101>,
> > + <0x00000064 0x01010001
> > 0x01010101>,
> > + <0x00000068 0x01010001
> > 0x01010101>,
> > + <0x0000006c 0x01010001
> > 0x01010101>,
> > + <0x00000070 0x01010001
> > 0x01010101>;
> > + bootph-all;
> > + };
> > +
> > + noc_fw_l4_sys_l4_sys_scr@ffd21100 {
> > + reg = <0xffd21100 0x00000098>;
> > + intel,offset-settings =
> > + /* Disable L4 system firewall */
> > + <0x00000008 0x01010001
> > 0x01010001>,
> > + <0x0000000c 0x01010001
> > 0x01010001>,
> > + <0x00000010 0x01010001
> > 0x01010001>,
> > + <0x00000014 0x01010001
> > 0x01010001>,
> > + <0x00000018 0x01010001
> > 0x01010001>,
> > + <0x0000001c 0x01010001
> > 0x01010001>,
> > + <0x00000020 0x01010001
> > 0x01010001>,
> > + <0x0000002c 0x01010001
> > 0x01010001>,
> > + <0x00000030 0x01010001
> > 0x01010001>,
> > + <0x00000034 0x01010001
> > 0x01010001>,
> > + <0x00000038 0x01010001
> > 0x01010001>,
> > + <0x00000040 0x01010001
> > 0x01010001>,
> > + <0x00000044 0x01010001
> > 0x01010001>,
> > + <0x00000048 0x01010001
> > 0x01010001>,
> > + <0x0000004c 0x01010001
> > 0x01010001>,
> > + <0x00000054 0x01010001
> > 0x01010001>,
> > + <0x00000058 0x01010001
> > 0x01010001>,
> > + <0x0000005c 0x01010001
> > 0x01010001>,
> > + <0x00000060 0x01010001
> > 0x01010101>,
> > + <0x00000064 0x01010001
> > 0x01010101>,
> > + <0x00000068 0x01010001
> > 0x01010101>,
> > + <0x0000006c 0x01010001
> > 0x01010101>,
> > + <0x00000070 0x01010001
> > 0x01010101>,
> > + <0x00000074 0x01010001
> > 0x01010101>,
> > + <0x00000078 0x01010001
> > 0x03010001>,
> > + <0x00000090 0x01010001
> > 0x01010001>,
> > + <0x00000094 0x01010001
> > 0x01010001>;
> > + bootph-all;
> > + };
> > +
> > + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {
> > + reg = <0xffd21200 0x00000004>;
> > + /* Disable soc2fpga security access */
> > + intel,offset-settings = <0x00000000
> > 0x0ffe0101 0x0ffe0101>;
> > + bootph-all;
> > + };
> > +
> > + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {
> > + reg = <0xffd21300 0x00000004>;
> > + /* Disable lightweight soc2fpga security
> > access */
> > + intel,offset-settings = <0x00000000
> > 0x0ffe0101 0x0ffe0101>;
> > + bootph-all;
> > + };
> > +
> > + noc_fw_tcu_tcu_scr@ffd21400 {
> > + reg = <0xffd21400 0x00000004>;
> > + /* Disable DMA ECC security access, for
> > SMMU use */
> > + intel,offset-settings = <0x00000000
> > 0x01010001 0x01010001>;
> > + bootph-all;
> > + };
> > +
> > + noc_fw_priv_MemoryMap_priv@ffd24800 {
> > + reg = <0xffd24800 0x0000000c>;
> > + intel,offset-settings =
> > + /* Enable non-prviledged access to
> > various periphs */
> > + <0x00000000 0xfff73ffb 0xfff73ffb>;
> > + bootph-all;
> > + };
> > + };
> > + };
> > +};
> > diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
> > b/arch/arm/dts/socfpga_stratix10.dtsi
> > old mode 100755
> > new mode 100644
> > diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> > b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> > old mode 100755
> > new mode 100644
> > diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> > b/arch/arm/dts/socfpga_stratix10_socdk.dts
> > old mode 100755
> > new mode 100644
> > --
> > 2.26.2
The fix is to solve checkpatch issue. Will submit S10 separately.
