[PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL

[Hal Feng]

From: Xingyu Wu <xingyu...@starfivetech.com>

Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu...@starfivetech.com>
Signed-off-by: Hal Feng <hal.f...@starfivetech.com>
---
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 +++---
 arch/riscv/dts/jh7110-u-boot.dtsi                | 1 -
 arch/riscv/dts/jh7110.dtsi                       | 8 ++++++--
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..fe8ae4ebee 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -305,9 +305,9 @@
                          <&syscrg JH7110_SYSCLK_BUS_ROOT>,
                          <&syscrg JH7110_SYSCLK_PERH_ROOT>,
                          <&syscrg JH7110_SYSCLK_QSPI_REF>;
-       assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
-                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
-                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+       assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL2_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL2_OUT>,
                                 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
        assigned-clock-rates = <0>, <0>, <0>, <0>;
 };
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi 
b/arch/riscv/dts/jh7110-u-boot.dtsi
index c22119518c..2f560e7296 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -83,7 +83,6 @@
 
 &syscrg {
        bootph-pre-ram;
-       starfive,sys-syscon = <&sys_syscon>;
 };
 
 &stgcrg {
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 3e5bddccc5..20433c766f 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -480,12 +480,16 @@
                                 <&gmac1_rgmii_rxin>,
                                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-                                <&tdm_ext>, <&mclk_ext>;
+                                <&tdm_ext>, <&mclk_ext>,
+                                <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL1_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL2_OUT>;
                        clock-names = "osc", "gmac1_rmii_refin",
                                      "gmac1_rgmii_rxin",
                                      "i2stx_bclk_ext", "i2stx_lrck_ext",
                                      "i2srx_bclk_ext", "i2srx_lrck_ext",
-                                     "tdm_ext", "mclk_ext";
+                                     "tdm_ext", "mclk_ext",
+                                     "pll0_out", "pll1_out", "pll2_out";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };
-- 
2.38.1