[PATCH 11/17] arm64: zynqmp: Add L2 cache nodes

[Michal Simek]

From: Radhey Shyam Pandey <radhey.shyam.pan...@amd.com>

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.

Reported-by: John Toomey <john.too...@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pan...@amd.com>
Signed-off-by: Michal Simek <michal.si...@amd.com>
---

 arch/arm/dts/zynqmp.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 38114d55386b..59b52919f130 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -33,6 +33,7 @@
                        operating-points-v2 = <&cpu_opp_table>;
                        reg = <0x0>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu1: cpu@1 {
@@ -42,6 +43,7 @@
                        reg = <0x1>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu2: cpu@2 {
@@ -51,6 +53,7 @@
                        reg = <0x2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu3: cpu@3 {
@@ -60,6 +63,13 @@
                        reg = <0x3>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
+               };
+
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
                };
 
                idle-states {
-- 
2.36.1