To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.
Signed-off-by: Nikhil M Jain <n-ja...@ti.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
---
V6:
- Add Reviewed-by tag.
V5:
- Change the layout of A53 SPL DDR into tabular format.
V4(patch introduced):
- Document A53 SPL DDR memory layout.
doc/board/ti/am62x_sk.rst | 57 +++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index 27d7b527c6..8642bdf16d 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -230,6 +230,63 @@ Image formats:
| +-------------------+ |
+-----------------------+
+A53 SPL DDR Memory Layout
+-------------------------
+
+This provides an overview memory usage in A53 SPL stage.
+
+.. list-table::
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Region
+ - Start Address
+ - End Address
+
+ * - EMPTY
+ - 0x80000000
+ - 0x80080000
+
+ * - TEXT BASE
+ - 0x80080000
+ - 0x800d8000
+
+ * - EMPTY
+ - 0x800d8000
+ - 0x80200000
+
+ * - BMP IMAGE
+ - 0x80200000
+ - 0x80b77660
+
+ * - STACK
+ - 0x80b77660
+ - 0x80b77e60
+
+ * - GD
+ - 0x80b77e60
+ - 0x80b78000
+
+ * - MALLOC
+ - 0x80b78000
+ - 0x80b80000
+
+ * - EMPTY
+ - 0x80b80000
+ - 0x80c80000
+
+ * - BSS
+ - 0x80c80000
+ - 0x80d00000
+
+ * - BLOBS
+ - 0x80d00000
+ - 0x80d00400
+
+ * - EMPTY
+ - 0x80d00400
+ - 0x81000000
+
Switch Setting for Boot Mode
----------------------------
--
2.34.1
