On 7/20/23 09:28, Ashok Reddy Soma wrote:
Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.s...@amd.com>
---
drivers/clk/clk_zynqmp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 27479391e1..b0843fe546 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -269,17 +269,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
case usb3_dual_ref:
return CRL_APB_USB3_DUAL_REF_CTRL;
case gem_tsu_ref:
+ case gem_tsu:
return CRL_APB_GEM_TSU_REF_CTRL;
case gem0_tx:
+ case gem0_rx:
case gem0_ref:
return CRL_APB_GEM0_REF_CTRL;
case gem1_tx:
+ case gem1_rx:
case gem1_ref:
return CRL_APB_GEM1_REF_CTRL;
case gem2_tx:
+ case gem2_rx:
case gem2_ref:
return CRL_APB_GEM2_REF_CTRL;
case gem3_tx:
+ case gem3_rx:
case gem3_ref:
return CRL_APB_GEM3_REF_CTRL;
case usb0_bus_ref:
Applied.
M
