On 2023/7/12 20:22, Jonas Karlman wrote:
The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") enabled SPI flash support by adding a spi0 alias.

Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and
SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.

Fixes: fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>

Thanks,
- Kever
---
  arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 1 -
  arch/arm/dts/rk3588s-u-boot.dtsi        | 9 +++++++++
  configs/rock5b-rk3588_defconfig         | 3 +++
  3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1cd8a57a6fa6..fc2825931a30 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,7 +11,6 @@
  / {
        aliases {
                mmc1 = &sdmmc;
-               spi0 = &sfc;
        };
chosen {
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index c703e41802b6..53b514ac52c0 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -7,6 +7,15 @@
  #include <dt-bindings/phy/phy.h>
/ {
+       aliases {
+               spi0 = &spi0;
+               spi1 = &spi1;
+               spi2 = &spi2;
+               spi3 = &spi3;
+               spi4 = &spi4;
+               spi5 = &sfc;
+       };
+
        dmc {
                compatible = "rockchip,rk3588-dmc";
                bootph-all;
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 17205a56cd99..f35886d9ffd1 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -56,6 +56,7 @@ CONFIG_CMD_REGULATOR=y
  CONFIG_SPL_OF_CONTROL=y
  CONFIG_OF_LIVE=y
  CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
  CONFIG_SPL_REGMAP=y
  CONFIG_SPL_SYSCON=y
  CONFIG_SPL_CLK=y
@@ -68,6 +69,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
  CONFIG_SPI_FLASH_MACRONIX=y
  CONFIG_SPI_FLASH_XTX=y
  CONFIG_ETH_DESIGNWARE=y

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