[PATCH v2 1/6] x86: Change tesing logic of mtrr commit

[Bin Meng]

From: Bin Meng <bmeng...@gmail.com>

On Coral U-Boot SPL programs some MTRRs and FSPv2 in U-Boot proper
needs to program MTRRs too. With current testing logic of mtrr
commit in init_cache_f_r(), the mtrr commit is skipped which won't
work as the queued mtrr requests include setup for DRAM regions.

Change the logic to allow such configuration.

Signed-off-by: Bin Meng <bmeng...@gmail.com>

---

Changes in v2:
- new patch: "x86: Change tesing logic of mtrr commit"

 arch/x86/lib/init_helpers.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index f33194045f..a2535e4468 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -14,15 +14,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int init_cache_f_r(void)
 {
-       bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
-                IS_ENABLED(CONFIG_FSP_VERSION2);
+       bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT);
        int ret;
 
        /*
         * Supported configurations:
         *
-        * booting from slimbootloader - in that case the MTRRs are already set
-        *      up
+        * booting from slimbootloader - MTRRs are already set up
         * booting with FSPv1 - MTRRs are already set up
         * booting with FSPv2 - MTRRs must be set here
         * booting from coreboot - in this case there is no SPL, so we set up
@@ -30,7 +28,7 @@ int init_cache_f_r(void)
         * Note: if there is an SPL, then it has already set up MTRRs so we
         *      don't need to do that here
         */
-       do_mtrr &= !IS_ENABLED(CONFIG_SPL) &&
+       do_mtrr &= (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_FSP_VERSION2)) 
&&
                !IS_ENABLED(CONFIG_FSP_VERSION1) &&
                !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
 
-- 
2.25.1