On 8/1/23 09:28, Eugen Hristev wrote:
From: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com>
[ Felipe: Ported from Linux kernel commit
f59dcab17629 ("usb: dwc3: core: improve reset sequence") ]
According to Synopsys Databook, we shouldn't be relying on
GCTL.CORESOFTRESET bit as that's only for debugging purposes.
Instead, let's use DCTL.CSFTRST if we're OTG or PERIPHERAL mode.
Host side block will be reset by XHCI driver if necessary. Note that this
reduces amount of time spent on dwc3_probe() by a long margin.
We're still gonna wait for reset to finish for a long time
(default to 1ms max), but tests show that the reset polling loop executed
at most 19 times (modprobe dwc3 && modprobe -r dwc3 executed 1000
times in a row).
Without proper core reset, observing random issues like when the
USB(DWC3) is in device mode, the host device is not able to detect the
USB device.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com>
[eugen.hris...@collabora.com: keep the PHY resets code]
Signed-off-by: Eugen Hristev <eugen.hris...@collabora.com>
NAK
---
Not to be merged, I know Marek does not apply any patches to DWC3.
That is not true and taken out of context.
What needs to happen is, someone needs to sync the DWC3 with Linux
instead of picking random subsets patches and turning the driver into a
total unmaintainable mess, which will be horribly difficult to sync in
the future due to these random patches mixed in the history. I explained
how to do it to Xilinx, it is a trivial thing to do, but it seems they
did not even bother to try the method.
